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#[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - control register"] pub cr: CR, #[doc = "0x04 - software trigger register"] pub swtrigr: SWTRIGR, #[doc = "0x08 - channel1 12-bit right-aligned data holding register"] pub dhr12r1: DHR12R1, #[doc = "0x0c - DAC channel1 12-bit left aligned data holding register"] pub dhr12l1: DHR12L1, #[doc = "0x10 - DAC channel1 8-bit right aligned data holding register"] pub dhr8r1: DHR8R1, _reserved5: [u8; 24usize], #[doc = "0x2c - DAC channel1 data output register"] pub dor1: DOR1, _reserved6: [u8; 4usize], #[doc = "0x34 - DAC status register"] pub sr: SR, } #[doc = "control register"] pub struct CR { register: vcell::VolatileCell<u32>, } #[doc = "control register"] pub mod cr; #[doc = "software trigger register"] pub struct SWTRIGR { register: vcell::VolatileCell<u32>, } #[doc = "software trigger register"] pub mod swtrigr; #[doc = "channel1 12-bit right-aligned data holding register"] pub struct DHR12R1 { register: vcell::VolatileCell<u32>, } #[doc = "channel1 12-bit right-aligned data holding register"] pub mod dhr12r1; #[doc = "DAC channel1 12-bit left aligned data holding register"] pub struct DHR12L1 { register: vcell::VolatileCell<u32>, } #[doc = "DAC channel1 12-bit left aligned data holding register"] pub mod dhr12l1; #[doc = "DAC channel1 8-bit right aligned data holding register"] pub struct DHR8R1 { register: vcell::VolatileCell<u32>, } #[doc = "DAC channel1 8-bit right aligned data holding register"] pub mod dhr8r1; #[doc = "DAC channel1 data output register"] pub struct DOR1 { register: vcell::VolatileCell<u32>, } #[doc = "DAC channel1 data output register"] pub mod dor1; #[doc = "DAC status register"] pub struct SR { register: vcell::VolatileCell<u32>, } #[doc = "DAC status register"] pub mod sr;