#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFGR2 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `PREDIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PREDIVR {
#[doc = "PREDIV input clock not divided"]
DIV1,
#[doc = "PREDIV input clock divided by 2"]
DIV2,
#[doc = "PREDIV input clock divided by 3"]
DIV3,
#[doc = "PREDIV input clock divided by 4"]
DIV4,
#[doc = "PREDIV input clock divided by 5"]
DIV5,
#[doc = "PREDIV input clock divided by 6"]
DIV6,
#[doc = "PREDIV input clock divided by 7"]
DIV7,
#[doc = "PREDIV input clock divided by 8"]
DIV8,
#[doc = "PREDIV input clock divided by 9"]
DIV9,
#[doc = "PREDIV input clock divided by 10"]
DIV10,
#[doc = "PREDIV input clock divided by 11"]
DIV11,
#[doc = "PREDIV input clock divided by 12"]
DIV12,
#[doc = "PREDIV input clock divided by 13"]
DIV13,
#[doc = "PREDIV input clock divided by 14"]
DIV14,
#[doc = "PREDIV input clock divided by 15"]
DIV15,
#[doc = "PREDIV input clock divided by 16"]
DIV16,
}
impl PREDIVR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
PREDIVR::DIV1 => 0,
PREDIVR::DIV2 => 0x01,
PREDIVR::DIV3 => 0x02,
PREDIVR::DIV4 => 0x03,
PREDIVR::DIV5 => 0x04,
PREDIVR::DIV6 => 0x05,
PREDIVR::DIV7 => 0x06,
PREDIVR::DIV8 => 0x07,
PREDIVR::DIV9 => 0x08,
PREDIVR::DIV10 => 0x09,
PREDIVR::DIV11 => 0x0a,
PREDIVR::DIV12 => 0x0b,
PREDIVR::DIV13 => 0x0c,
PREDIVR::DIV14 => 0x0d,
PREDIVR::DIV15 => 0x0e,
PREDIVR::DIV16 => 0x0f,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> PREDIVR {
match value {
0 => PREDIVR::DIV1,
1 => PREDIVR::DIV2,
2 => PREDIVR::DIV3,
3 => PREDIVR::DIV4,
4 => PREDIVR::DIV5,
5 => PREDIVR::DIV6,
6 => PREDIVR::DIV7,
7 => PREDIVR::DIV8,
8 => PREDIVR::DIV9,
9 => PREDIVR::DIV10,
10 => PREDIVR::DIV11,
11 => PREDIVR::DIV12,
12 => PREDIVR::DIV13,
13 => PREDIVR::DIV14,
14 => PREDIVR::DIV15,
15 => PREDIVR::DIV16,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DIV1`"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == PREDIVR::DIV1
}
#[doc = "Checks if the value of the field is `DIV2`"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == PREDIVR::DIV2
}
#[doc = "Checks if the value of the field is `DIV3`"]
#[inline(always)]
pub fn is_div3(&self) -> bool {
*self == PREDIVR::DIV3
}
#[doc = "Checks if the value of the field is `DIV4`"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == PREDIVR::DIV4
}
#[doc = "Checks if the value of the field is `DIV5`"]
#[inline(always)]
pub fn is_div5(&self) -> bool {
*self == PREDIVR::DIV5
}
#[doc = "Checks if the value of the field is `DIV6`"]
#[inline(always)]
pub fn is_div6(&self) -> bool {
*self == PREDIVR::DIV6
}
#[doc = "Checks if the value of the field is `DIV7`"]
#[inline(always)]
pub fn is_div7(&self) -> bool {
*self == PREDIVR::DIV7
}
#[doc = "Checks if the value of the field is `DIV8`"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == PREDIVR::DIV8
}
#[doc = "Checks if the value of the field is `DIV9`"]
#[inline(always)]
pub fn is_div9(&self) -> bool {
*self == PREDIVR::DIV9
}
#[doc = "Checks if the value of the field is `DIV10`"]
#[inline(always)]
pub fn is_div10(&self) -> bool {
*self == PREDIVR::DIV10
}
#[doc = "Checks if the value of the field is `DIV11`"]
#[inline(always)]
pub fn is_div11(&self) -> bool {
*self == PREDIVR::DIV11
}
#[doc = "Checks if the value of the field is `DIV12`"]
#[inline(always)]
pub fn is_div12(&self) -> bool {
*self == PREDIVR::DIV12
}
#[doc = "Checks if the value of the field is `DIV13`"]
#[inline(always)]
pub fn is_div13(&self) -> bool {
*self == PREDIVR::DIV13
}
#[doc = "Checks if the value of the field is `DIV14`"]
#[inline(always)]
pub fn is_div14(&self) -> bool {
*self == PREDIVR::DIV14
}
#[doc = "Checks if the value of the field is `DIV15`"]
#[inline(always)]
pub fn is_div15(&self) -> bool {
*self == PREDIVR::DIV15
}
#[doc = "Checks if the value of the field is `DIV16`"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == PREDIVR::DIV16
}
}
#[doc = "Values that can be written to the field `PREDIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PREDIVW {
#[doc = "PREDIV input clock not divided"]
DIV1,
#[doc = "PREDIV input clock divided by 2"]
DIV2,
#[doc = "PREDIV input clock divided by 3"]
DIV3,
#[doc = "PREDIV input clock divided by 4"]
DIV4,
#[doc = "PREDIV input clock divided by 5"]
DIV5,
#[doc = "PREDIV input clock divided by 6"]
DIV6,
#[doc = "PREDIV input clock divided by 7"]
DIV7,
#[doc = "PREDIV input clock divided by 8"]
DIV8,
#[doc = "PREDIV input clock divided by 9"]
DIV9,
#[doc = "PREDIV input clock divided by 10"]
DIV10,
#[doc = "PREDIV input clock divided by 11"]
DIV11,
#[doc = "PREDIV input clock divided by 12"]
DIV12,
#[doc = "PREDIV input clock divided by 13"]
DIV13,
#[doc = "PREDIV input clock divided by 14"]
DIV14,
#[doc = "PREDIV input clock divided by 15"]
DIV15,
#[doc = "PREDIV input clock divided by 16"]
DIV16,
}
impl PREDIVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
PREDIVW::DIV1 => 0,
PREDIVW::DIV2 => 1,
PREDIVW::DIV3 => 2,
PREDIVW::DIV4 => 3,
PREDIVW::DIV5 => 4,
PREDIVW::DIV6 => 5,
PREDIVW::DIV7 => 6,
PREDIVW::DIV8 => 7,
PREDIVW::DIV9 => 8,
PREDIVW::DIV10 => 9,
PREDIVW::DIV11 => 10,
PREDIVW::DIV12 => 11,
PREDIVW::DIV13 => 12,
PREDIVW::DIV14 => 13,
PREDIVW::DIV15 => 14,
PREDIVW::DIV16 => 15,
}
}
}
#[doc = r"Proxy"]
pub struct _PREDIVW<'a> {
w: &'a mut W,
}
impl<'a> _PREDIVW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PREDIVW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "PREDIV input clock not divided"]
#[inline(always)]
pub fn div1(self) -> &'a mut W {
self.variant(PREDIVW::DIV1)
}
#[doc = "PREDIV input clock divided by 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut W {
self.variant(PREDIVW::DIV2)
}
#[doc = "PREDIV input clock divided by 3"]
#[inline(always)]
pub fn div3(self) -> &'a mut W {
self.variant(PREDIVW::DIV3)
}
#[doc = "PREDIV input clock divided by 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut W {
self.variant(PREDIVW::DIV4)
}
#[doc = "PREDIV input clock divided by 5"]
#[inline(always)]
pub fn div5(self) -> &'a mut W {
self.variant(PREDIVW::DIV5)
}
#[doc = "PREDIV input clock divided by 6"]
#[inline(always)]
pub fn div6(self) -> &'a mut W {
self.variant(PREDIVW::DIV6)
}
#[doc = "PREDIV input clock divided by 7"]
#[inline(always)]
pub fn div7(self) -> &'a mut W {
self.variant(PREDIVW::DIV7)
}
#[doc = "PREDIV input clock divided by 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut W {
self.variant(PREDIVW::DIV8)
}
#[doc = "PREDIV input clock divided by 9"]
#[inline(always)]
pub fn div9(self) -> &'a mut W {
self.variant(PREDIVW::DIV9)
}
#[doc = "PREDIV input clock divided by 10"]
#[inline(always)]
pub fn div10(self) -> &'a mut W {
self.variant(PREDIVW::DIV10)
}
#[doc = "PREDIV input clock divided by 11"]
#[inline(always)]
pub fn div11(self) -> &'a mut W {
self.variant(PREDIVW::DIV11)
}
#[doc = "PREDIV input clock divided by 12"]
#[inline(always)]
pub fn div12(self) -> &'a mut W {
self.variant(PREDIVW::DIV12)
}
#[doc = "PREDIV input clock divided by 13"]
#[inline(always)]
pub fn div13(self) -> &'a mut W {
self.variant(PREDIVW::DIV13)
}
#[doc = "PREDIV input clock divided by 14"]
#[inline(always)]
pub fn div14(self) -> &'a mut W {
self.variant(PREDIVW::DIV14)
}
#[doc = "PREDIV input clock divided by 15"]
#[inline(always)]
pub fn div15(self) -> &'a mut W {
self.variant(PREDIVW::DIV15)
}
#[doc = "PREDIV input clock divided by 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut W {
self.variant(PREDIVW::DIV16)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x0f << 0);
self.w.bits |= ((value as u32) & 0x0f) << 0;
self.w
}
}
#[doc = "Possible values of the field `ADC12PRES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC12PRESR {
#[doc = "No clock"]
NOCLOCK,
#[doc = "PLL clock not divided"]
DIV1,
#[doc = "PLL clock divided by 2"]
DIV2,
#[doc = "PLL clock divided by 4"]
DIV4,
#[doc = "PLL clock divided by 6"]
DIV6,
#[doc = "PLL clock divided by 8"]
DIV8,
#[doc = "PLL clock divided by 10"]
DIV10,
#[doc = "PLL clock divided by 12"]
DIV12,
#[doc = "PLL clock divided by 16"]
DIV16,
#[doc = "PLL clock divided by 32"]
DIV32,
#[doc = "PLL clock divided by 64"]
DIV64,
#[doc = "PLL clock divided by 128"]
DIV128,
#[doc = "PLL clock divided by 256"]
DIV256,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl ADC12PRESR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
ADC12PRESR::NOCLOCK => 0,
ADC12PRESR::DIV1 => 0x10,
ADC12PRESR::DIV2 => 0x11,
ADC12PRESR::DIV4 => 0x12,
ADC12PRESR::DIV6 => 0x13,
ADC12PRESR::DIV8 => 0x14,
ADC12PRESR::DIV10 => 0x15,
ADC12PRESR::DIV12 => 0x16,
ADC12PRESR::DIV16 => 0x17,
ADC12PRESR::DIV32 => 0x18,
ADC12PRESR::DIV64 => 0x19,
ADC12PRESR::DIV128 => 0x1a,
ADC12PRESR::DIV256 => 0x1b,
ADC12PRESR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> ADC12PRESR {
match value {
0 => ADC12PRESR::NOCLOCK,
16 => ADC12PRESR::DIV1,
17 => ADC12PRESR::DIV2,
18 => ADC12PRESR::DIV4,
19 => ADC12PRESR::DIV6,
20 => ADC12PRESR::DIV8,
21 => ADC12PRESR::DIV10,
22 => ADC12PRESR::DIV12,
23 => ADC12PRESR::DIV16,
24 => ADC12PRESR::DIV32,
25 => ADC12PRESR::DIV64,
26 => ADC12PRESR::DIV128,
27 => ADC12PRESR::DIV256,
i => ADC12PRESR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `NOCLOCK`"]
#[inline(always)]
pub fn is_no_clock(&self) -> bool {
*self == ADC12PRESR::NOCLOCK
}
#[doc = "Checks if the value of the field is `DIV1`"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == ADC12PRESR::DIV1
}
#[doc = "Checks if the value of the field is `DIV2`"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == ADC12PRESR::DIV2
}
#[doc = "Checks if the value of the field is `DIV4`"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == ADC12PRESR::DIV4
}
#[doc = "Checks if the value of the field is `DIV6`"]
#[inline(always)]
pub fn is_div6(&self) -> bool {
*self == ADC12PRESR::DIV6
}
#[doc = "Checks if the value of the field is `DIV8`"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == ADC12PRESR::DIV8
}
#[doc = "Checks if the value of the field is `DIV10`"]
#[inline(always)]
pub fn is_div10(&self) -> bool {
*self == ADC12PRESR::DIV10
}
#[doc = "Checks if the value of the field is `DIV12`"]
#[inline(always)]
pub fn is_div12(&self) -> bool {
*self == ADC12PRESR::DIV12
}
#[doc = "Checks if the value of the field is `DIV16`"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == ADC12PRESR::DIV16
}
#[doc = "Checks if the value of the field is `DIV32`"]
#[inline(always)]
pub fn is_div32(&self) -> bool {
*self == ADC12PRESR::DIV32
}
#[doc = "Checks if the value of the field is `DIV64`"]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == ADC12PRESR::DIV64
}
#[doc = "Checks if the value of the field is `DIV128`"]
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == ADC12PRESR::DIV128
}
#[doc = "Checks if the value of the field is `DIV256`"]
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == ADC12PRESR::DIV256
}
}
#[doc = "Values that can be written to the field `ADC12PRES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC12PRESW {
#[doc = "No clock"]
NOCLOCK,
#[doc = "PLL clock not divided"]
DIV1,
#[doc = "PLL clock divided by 2"]
DIV2,
#[doc = "PLL clock divided by 4"]
DIV4,
#[doc = "PLL clock divided by 6"]
DIV6,
#[doc = "PLL clock divided by 8"]
DIV8,
#[doc = "PLL clock divided by 10"]
DIV10,
#[doc = "PLL clock divided by 12"]
DIV12,
#[doc = "PLL clock divided by 16"]
DIV16,
#[doc = "PLL clock divided by 32"]
DIV32,
#[doc = "PLL clock divided by 64"]
DIV64,
#[doc = "PLL clock divided by 128"]
DIV128,
#[doc = "PLL clock divided by 256"]
DIV256,
}
impl ADC12PRESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
ADC12PRESW::NOCLOCK => 0,
ADC12PRESW::DIV1 => 16,
ADC12PRESW::DIV2 => 17,
ADC12PRESW::DIV4 => 18,
ADC12PRESW::DIV6 => 19,
ADC12PRESW::DIV8 => 20,
ADC12PRESW::DIV10 => 21,
ADC12PRESW::DIV12 => 22,
ADC12PRESW::DIV16 => 23,
ADC12PRESW::DIV32 => 24,
ADC12PRESW::DIV64 => 25,
ADC12PRESW::DIV128 => 26,
ADC12PRESW::DIV256 => 27,
}
}
}
#[doc = r"Proxy"]
pub struct _ADC12PRESW<'a> {
w: &'a mut W,
}
impl<'a> _ADC12PRESW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ADC12PRESW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "No clock"]
#[inline(always)]
pub fn no_clock(self) -> &'a mut W {
self.variant(ADC12PRESW::NOCLOCK)
}
#[doc = "PLL clock not divided"]
#[inline(always)]
pub fn div1(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV1)
}
#[doc = "PLL clock divided by 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV2)
}
#[doc = "PLL clock divided by 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV4)
}
#[doc = "PLL clock divided by 6"]
#[inline(always)]
pub fn div6(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV6)
}
#[doc = "PLL clock divided by 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV8)
}
#[doc = "PLL clock divided by 10"]
#[inline(always)]
pub fn div10(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV10)
}
#[doc = "PLL clock divided by 12"]
#[inline(always)]
pub fn div12(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV12)
}
#[doc = "PLL clock divided by 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV16)
}
#[doc = "PLL clock divided by 32"]
#[inline(always)]
pub fn div32(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV32)
}
#[doc = "PLL clock divided by 64"]
#[inline(always)]
pub fn div64(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV64)
}
#[doc = "PLL clock divided by 128"]
#[inline(always)]
pub fn div128(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV128)
}
#[doc = "PLL clock divided by 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV256)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 4);
self.w.bits |= ((value as u32) & 0x1f) << 4;
self.w
}
}
#[doc = "Possible values of the field `ADC34PRES`"]
pub type ADC34PRESR = ADC12PRESR;
#[doc = "Values that can be written to the field `ADC34PRES`"]
pub type ADC34PRESW = ADC12PRESW;
#[doc = r"Proxy"]
pub struct _ADC34PRESW<'a> {
w: &'a mut W,
}
impl<'a> _ADC34PRESW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ADC34PRESW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "No clock"]
#[inline(always)]
pub fn no_clock(self) -> &'a mut W {
self.variant(ADC12PRESW::NOCLOCK)
}
#[doc = "PLL clock not divided"]
#[inline(always)]
pub fn div1(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV1)
}
#[doc = "PLL clock divided by 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV2)
}
#[doc = "PLL clock divided by 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV4)
}
#[doc = "PLL clock divided by 6"]
#[inline(always)]
pub fn div6(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV6)
}
#[doc = "PLL clock divided by 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV8)
}
#[doc = "PLL clock divided by 10"]
#[inline(always)]
pub fn div10(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV10)
}
#[doc = "PLL clock divided by 12"]
#[inline(always)]
pub fn div12(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV12)
}
#[doc = "PLL clock divided by 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV16)
}
#[doc = "PLL clock divided by 32"]
#[inline(always)]
pub fn div32(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV32)
}
#[doc = "PLL clock divided by 64"]
#[inline(always)]
pub fn div64(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV64)
}
#[doc = "PLL clock divided by 128"]
#[inline(always)]
pub fn div128(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV128)
}
#[doc = "PLL clock divided by 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut W {
self.variant(ADC12PRESW::DIV256)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 9);
self.w.bits |= ((value as u32) & 0x1f) << 9;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - PREDIV division factor"]
#[inline(always)]
pub fn prediv(&self) -> PREDIVR {
PREDIVR::_from(((self.bits >> 0) & 0x0f) as u8)
}
#[doc = "Bits 4:8 - ADC1 and ADC2 prescaler"]
#[inline(always)]
pub fn adc12pres(&self) -> ADC12PRESR {
ADC12PRESR::_from(((self.bits >> 4) & 0x1f) as u8)
}
#[doc = "Bits 9:13 - ADC3 and ADC4 prescaler"]
#[inline(always)]
pub fn adc34pres(&self) -> ADC34PRESR {
ADC34PRESR::_from(((self.bits >> 9) & 0x1f) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - PREDIV division factor"]
#[inline(always)]
pub fn prediv(&mut self) -> _PREDIVW {
_PREDIVW { w: self }
}
#[doc = "Bits 4:8 - ADC1 and ADC2 prescaler"]
#[inline(always)]
pub fn adc12pres(&mut self) -> _ADC12PRESW {
_ADC12PRESW { w: self }
}
#[doc = "Bits 9:13 - ADC3 and ADC4 prescaler"]
#[inline(always)]
pub fn adc34pres(&mut self) -> _ADC34PRESW {
_ADC34PRESW { w: self }
}
}