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#[doc = r" Value read from the register"] pub struct R { bits: u32, } #[doc = r" Value to write to the register"] pub struct W { bits: u32, } impl super::SYSCFG_CFGR3 { #[doc = r" Modifies the contents of the register"] #[inline] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); let r = R { bits: bits }; let mut w = W { bits: bits }; f(&r, &mut w); self.register.set(w.bits); } #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r" Writes to the register"] #[inline] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { let mut w = W::reset_value(); f(&mut w); self.register.set(w.bits); } #[doc = r" Writes the reset value to the register"] #[inline] pub fn reset(&self) { self.write(|w| w) } } #[doc = r" Value of the field"] pub struct DAC1_TRIG5_RMPR { bits: bool, } impl DAC1_TRIG5_RMPR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bit(&self) -> bool { self.bits } #[doc = r" Returns `true` if the bit is clear (0)"] #[inline] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r" Returns `true` if the bit is set (1)"] #[inline] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r" Value of the field"] pub struct DAC1_TRIG3_RMPR { bits: bool, } impl DAC1_TRIG3_RMPR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bit(&self) -> bool { self.bits } #[doc = r" Returns `true` if the bit is clear (0)"] #[inline] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r" Returns `true` if the bit is set (1)"] #[inline] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r" Value of the field"] pub struct ADC2_DMA_RMP_1R { bits: bool, } impl ADC2_DMA_RMP_1R { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bit(&self) -> bool { self.bits } #[doc = r" Returns `true` if the bit is clear (0)"] #[inline] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r" Returns `true` if the bit is set (1)"] #[inline] pub fn bit_is_set(&self) -> bool { self.bit() } } #[doc = r" Value of the field"] pub struct ADC2_DMA_RMP_0R { bits: u8, } impl ADC2_DMA_RMP_0R { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u8 { self.bits } } #[doc = r" Value of the field"] pub struct I2C1_RX_DMA_RMPR { bits: u8, } impl I2C1_RX_DMA_RMPR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u8 { self.bits } } #[doc = r" Value of the field"] pub struct SPI1_TX_DMA_RMPR { bits: u8, } impl SPI1_TX_DMA_RMPR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u8 { self.bits } } #[doc = r" Value of the field"] pub struct SPI1_RX_DMA_RMPR { bits: u8, } impl SPI1_RX_DMA_RMPR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u8 { self.bits } } #[doc = r" Proxy"] pub struct _DAC1_TRIG5_RMPW<'a> { w: &'a mut W, } impl<'a> _DAC1_TRIG5_RMPW<'a> { #[doc = r" Sets the field bit"] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r" Writes raw bits to the field"] #[inline] pub fn bit(self, value: bool) -> &'a mut W { const MASK: bool = true; const OFFSET: u8 = 17; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _DAC1_TRIG3_RMPW<'a> { w: &'a mut W, } impl<'a> _DAC1_TRIG3_RMPW<'a> { #[doc = r" Sets the field bit"] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r" Writes raw bits to the field"] #[inline] pub fn bit(self, value: bool) -> &'a mut W { const MASK: bool = true; const OFFSET: u8 = 16; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _ADC2_DMA_RMP_1W<'a> { w: &'a mut W, } impl<'a> _ADC2_DMA_RMP_1W<'a> { #[doc = r" Sets the field bit"] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r" Writes raw bits to the field"] #[inline] pub fn bit(self, value: bool) -> &'a mut W { const MASK: bool = true; const OFFSET: u8 = 9; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _ADC2_DMA_RMP_0W<'a> { w: &'a mut W, } impl<'a> _ADC2_DMA_RMP_0W<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u8) -> &'a mut W { const MASK: u8 = 3; const OFFSET: u8 = 6; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _I2C1_RX_DMA_RMPW<'a> { w: &'a mut W, } impl<'a> _I2C1_RX_DMA_RMPW<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u8) -> &'a mut W { const MASK: u8 = 3; const OFFSET: u8 = 4; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _SPI1_TX_DMA_RMPW<'a> { w: &'a mut W, } impl<'a> _SPI1_TX_DMA_RMPW<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u8) -> &'a mut W { const MASK: u8 = 3; const OFFSET: u8 = 2; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } #[doc = r" Proxy"] pub struct _SPI1_RX_DMA_RMPW<'a> { w: &'a mut W, } impl<'a> _SPI1_RX_DMA_RMPW<'a> { #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u8) -> &'a mut W { const MASK: u8 = 3; const OFFSET: u8 = 0; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } impl R { #[doc = r" Value of the register as raw bits"] #[inline] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bit 17 - DAC1_CH1 / DAC1_CH2 Trigger remap"] #[inline] pub fn dac1_trig5_rmp(&self) -> DAC1_TRIG5_RMPR { let bits = { const MASK: bool = true; const OFFSET: u8 = 17; ((self.bits >> OFFSET) & MASK as u32) != 0 }; DAC1_TRIG5_RMPR { bits } } #[doc = "Bit 16 - DAC1_CH1 / DAC1_CH2 Trigger remap"] #[inline] pub fn dac1_trig3_rmp(&self) -> DAC1_TRIG3_RMPR { let bits = { const MASK: bool = true; const OFFSET: u8 = 16; ((self.bits >> OFFSET) & MASK as u32) != 0 }; DAC1_TRIG3_RMPR { bits } } #[doc = "Bit 9 - ADC2 DMA controller remapping bit"] #[inline] pub fn adc2_dma_rmp_1(&self) -> ADC2_DMA_RMP_1R { let bits = { const MASK: bool = true; const OFFSET: u8 = 9; ((self.bits >> OFFSET) & MASK as u32) != 0 }; ADC2_DMA_RMP_1R { bits } } #[doc = "Bits 6:7 - ADC2 DMA channel remapping bit"] #[inline] pub fn adc2_dma_rmp_0(&self) -> ADC2_DMA_RMP_0R { let bits = { const MASK: u8 = 3; const OFFSET: u8 = 6; ((self.bits >> OFFSET) & MASK as u32) as u8 }; ADC2_DMA_RMP_0R { bits } } #[doc = "Bits 4:5 - I2C1_RX DMA remapping bit"] #[inline] pub fn i2c1_rx_dma_rmp(&self) -> I2C1_RX_DMA_RMPR { let bits = { const MASK: u8 = 3; const OFFSET: u8 = 4; ((self.bits >> OFFSET) & MASK as u32) as u8 }; I2C1_RX_DMA_RMPR { bits } } #[doc = "Bits 2:3 - SPI1_TX DMA remapping bit"] #[inline] pub fn spi1_tx_dma_rmp(&self) -> SPI1_TX_DMA_RMPR { let bits = { const MASK: u8 = 3; const OFFSET: u8 = 2; ((self.bits >> OFFSET) & MASK as u32) as u8 }; SPI1_TX_DMA_RMPR { bits } } #[doc = "Bits 0:1 - SPI1_RX DMA remapping bit"] #[inline] pub fn spi1_rx_dma_rmp(&self) -> SPI1_RX_DMA_RMPR { let bits = { const MASK: u8 = 3; const OFFSET: u8 = 0; ((self.bits >> OFFSET) & MASK as u32) as u8 }; SPI1_RX_DMA_RMPR { bits } } } impl W { #[doc = r" Reset value of the register"] #[inline] pub fn reset_value() -> W { W { bits: 0 } } #[doc = r" Writes raw bits to the register"] #[inline] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bit 17 - DAC1_CH1 / DAC1_CH2 Trigger remap"] #[inline] pub fn dac1_trig5_rmp(&mut self) -> _DAC1_TRIG5_RMPW { _DAC1_TRIG5_RMPW { w: self } } #[doc = "Bit 16 - DAC1_CH1 / DAC1_CH2 Trigger remap"] #[inline] pub fn dac1_trig3_rmp(&mut self) -> _DAC1_TRIG3_RMPW { _DAC1_TRIG3_RMPW { w: self } } #[doc = "Bit 9 - ADC2 DMA controller remapping bit"] #[inline] pub fn adc2_dma_rmp_1(&mut self) -> _ADC2_DMA_RMP_1W { _ADC2_DMA_RMP_1W { w: self } } #[doc = "Bits 6:7 - ADC2 DMA channel remapping bit"] #[inline] pub fn adc2_dma_rmp_0(&mut self) -> _ADC2_DMA_RMP_0W { _ADC2_DMA_RMP_0W { w: self } } #[doc = "Bits 4:5 - I2C1_RX DMA remapping bit"] #[inline] pub fn i2c1_rx_dma_rmp(&mut self) -> _I2C1_RX_DMA_RMPW { _I2C1_RX_DMA_RMPW { w: self } } #[doc = "Bits 2:3 - SPI1_TX DMA remapping bit"] #[inline] pub fn spi1_tx_dma_rmp(&mut self) -> _SPI1_TX_DMA_RMPW { _SPI1_TX_DMA_RMPW { w: self } } #[doc = "Bits 0:1 - SPI1_RX DMA remapping bit"] #[inline] pub fn spi1_rx_dma_rmp(&mut self) -> _SPI1_RX_DMA_RMPW { _SPI1_RX_DMA_RMPW { w: self } } }