stm32f3/stm32f302/adc1_2/
cdr.rs

1///Register `CDR` reader
2pub type R = crate::R<CDRrs>;
3///Field `RDATA_MST` reader - Regular data of the master ADC
4pub type RDATA_MST_R = crate::FieldReader<u16>;
5///Field `RDATA_SLV` reader - Regular data of the slave ADC
6pub type RDATA_SLV_R = crate::FieldReader<u16>;
7impl R {
8    ///Bits 0:15 - Regular data of the master ADC
9    #[inline(always)]
10    pub fn rdata_mst(&self) -> RDATA_MST_R {
11        RDATA_MST_R::new((self.bits & 0xffff) as u16)
12    }
13    ///Bits 16:31 - Regular data of the slave ADC
14    #[inline(always)]
15    pub fn rdata_slv(&self) -> RDATA_SLV_R {
16        RDATA_SLV_R::new(((self.bits >> 16) & 0xffff) as u16)
17    }
18}
19impl core::fmt::Debug for R {
20    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21        f.debug_struct("CDR")
22            .field("rdata_slv", &self.rdata_slv())
23            .field("rdata_mst", &self.rdata_mst())
24            .finish()
25    }
26}
27/**ADC common regular data register for dual and triple modes
28
29You can [`read`](crate::Reg::read) this register and get [`cdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
30
31See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#ADC1_2:CDR)*/
32pub struct CDRrs;
33impl crate::RegisterSpec for CDRrs {
34    type Ux = u32;
35}
36///`read()` method returns [`cdr::R`](R) reader structure
37impl crate::Readable for CDRrs {}
38///`reset()` method sets CDR to value 0
39impl crate::Resettable for CDRrs {}
stm32f3/stm32f302/adc1_2/cdr.rs

stm32f3/stm32f302/adc1_2/
cdr.rs
