stm32f3/stm32f303/fpu/
fpscr.rs1#[doc = "Register `FPSCR` reader"]
2pub struct R(crate::R<FPSCR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<FPSCR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<FPSCR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<FPSCR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `FPSCR` writer"]
17pub struct W(crate::W<FPSCR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<FPSCR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<FPSCR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<FPSCR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `IOC` reader - Invalid operation cumulative exception bit"]
38pub type IOC_R = crate::BitReader<bool>;
39#[doc = "Field `IOC` writer - Invalid operation cumulative exception bit"]
40pub type IOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
41#[doc = "Field `DZC` reader - Division by zero cumulative exception bit."]
42pub type DZC_R = crate::BitReader<bool>;
43#[doc = "Field `DZC` writer - Division by zero cumulative exception bit."]
44pub type DZC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
45#[doc = "Field `OFC` reader - Overflow cumulative exception bit"]
46pub type OFC_R = crate::BitReader<bool>;
47#[doc = "Field `OFC` writer - Overflow cumulative exception bit"]
48pub type OFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
49#[doc = "Field `UFC` reader - Underflow cumulative exception bit"]
50pub type UFC_R = crate::BitReader<bool>;
51#[doc = "Field `UFC` writer - Underflow cumulative exception bit"]
52pub type UFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
53#[doc = "Field `IXC` reader - Inexact cumulative exception bit"]
54pub type IXC_R = crate::BitReader<bool>;
55#[doc = "Field `IXC` writer - Inexact cumulative exception bit"]
56pub type IXC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
57#[doc = "Field `IDC` reader - Input denormal cumulative exception bit."]
58pub type IDC_R = crate::BitReader<bool>;
59#[doc = "Field `IDC` writer - Input denormal cumulative exception bit."]
60pub type IDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
61#[doc = "Field `RMode` reader - Rounding Mode control field"]
62pub type RMODE_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `RMode` writer - Rounding Mode control field"]
64pub type RMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FPSCR_SPEC, u8, u8, 2, O>;
65#[doc = "Field `FZ` reader - Flush-to-zero mode control bit:"]
66pub type FZ_R = crate::BitReader<bool>;
67#[doc = "Field `FZ` writer - Flush-to-zero mode control bit:"]
68pub type FZ_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
69#[doc = "Field `DN` reader - Default NaN mode control bit"]
70pub type DN_R = crate::BitReader<bool>;
71#[doc = "Field `DN` writer - Default NaN mode control bit"]
72pub type DN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
73#[doc = "Field `AHP` reader - Alternative half-precision control bit"]
74pub type AHP_R = crate::BitReader<bool>;
75#[doc = "Field `AHP` writer - Alternative half-precision control bit"]
76pub type AHP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
77#[doc = "Field `V` reader - Overflow condition code flag"]
78pub type V_R = crate::BitReader<bool>;
79#[doc = "Field `V` writer - Overflow condition code flag"]
80pub type V_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
81#[doc = "Field `C` reader - Carry condition code flag"]
82pub type C_R = crate::BitReader<bool>;
83#[doc = "Field `C` writer - Carry condition code flag"]
84pub type C_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
85#[doc = "Field `Z` reader - Zero condition code flag"]
86pub type Z_R = crate::BitReader<bool>;
87#[doc = "Field `Z` writer - Zero condition code flag"]
88pub type Z_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
89#[doc = "Field `N` reader - Negative condition code flag"]
90pub type N_R = crate::BitReader<bool>;
91#[doc = "Field `N` writer - Negative condition code flag"]
92pub type N_W<'a, const O: u8> = crate::BitWriter<'a, u32, FPSCR_SPEC, bool, O>;
93impl R {
94 #[doc = "Bit 0 - Invalid operation cumulative exception bit"]
95 #[inline(always)]
96 pub fn ioc(&self) -> IOC_R {
97 IOC_R::new((self.bits & 1) != 0)
98 }
99 #[doc = "Bit 1 - Division by zero cumulative exception bit."]
100 #[inline(always)]
101 pub fn dzc(&self) -> DZC_R {
102 DZC_R::new(((self.bits >> 1) & 1) != 0)
103 }
104 #[doc = "Bit 2 - Overflow cumulative exception bit"]
105 #[inline(always)]
106 pub fn ofc(&self) -> OFC_R {
107 OFC_R::new(((self.bits >> 2) & 1) != 0)
108 }
109 #[doc = "Bit 3 - Underflow cumulative exception bit"]
110 #[inline(always)]
111 pub fn ufc(&self) -> UFC_R {
112 UFC_R::new(((self.bits >> 3) & 1) != 0)
113 }
114 #[doc = "Bit 4 - Inexact cumulative exception bit"]
115 #[inline(always)]
116 pub fn ixc(&self) -> IXC_R {
117 IXC_R::new(((self.bits >> 4) & 1) != 0)
118 }
119 #[doc = "Bit 7 - Input denormal cumulative exception bit."]
120 #[inline(always)]
121 pub fn idc(&self) -> IDC_R {
122 IDC_R::new(((self.bits >> 7) & 1) != 0)
123 }
124 #[doc = "Bits 22:23 - Rounding Mode control field"]
125 #[inline(always)]
126 pub fn rmode(&self) -> RMODE_R {
127 RMODE_R::new(((self.bits >> 22) & 3) as u8)
128 }
129 #[doc = "Bit 24 - Flush-to-zero mode control bit:"]
130 #[inline(always)]
131 pub fn fz(&self) -> FZ_R {
132 FZ_R::new(((self.bits >> 24) & 1) != 0)
133 }
134 #[doc = "Bit 25 - Default NaN mode control bit"]
135 #[inline(always)]
136 pub fn dn(&self) -> DN_R {
137 DN_R::new(((self.bits >> 25) & 1) != 0)
138 }
139 #[doc = "Bit 26 - Alternative half-precision control bit"]
140 #[inline(always)]
141 pub fn ahp(&self) -> AHP_R {
142 AHP_R::new(((self.bits >> 26) & 1) != 0)
143 }
144 #[doc = "Bit 28 - Overflow condition code flag"]
145 #[inline(always)]
146 pub fn v(&self) -> V_R {
147 V_R::new(((self.bits >> 28) & 1) != 0)
148 }
149 #[doc = "Bit 29 - Carry condition code flag"]
150 #[inline(always)]
151 pub fn c(&self) -> C_R {
152 C_R::new(((self.bits >> 29) & 1) != 0)
153 }
154 #[doc = "Bit 30 - Zero condition code flag"]
155 #[inline(always)]
156 pub fn z(&self) -> Z_R {
157 Z_R::new(((self.bits >> 30) & 1) != 0)
158 }
159 #[doc = "Bit 31 - Negative condition code flag"]
160 #[inline(always)]
161 pub fn n(&self) -> N_R {
162 N_R::new(((self.bits >> 31) & 1) != 0)
163 }
164}
165impl W {
166 #[doc = "Bit 0 - Invalid operation cumulative exception bit"]
167 #[inline(always)]
168 pub fn ioc(&mut self) -> IOC_W<0> {
169 IOC_W::new(self)
170 }
171 #[doc = "Bit 1 - Division by zero cumulative exception bit."]
172 #[inline(always)]
173 pub fn dzc(&mut self) -> DZC_W<1> {
174 DZC_W::new(self)
175 }
176 #[doc = "Bit 2 - Overflow cumulative exception bit"]
177 #[inline(always)]
178 pub fn ofc(&mut self) -> OFC_W<2> {
179 OFC_W::new(self)
180 }
181 #[doc = "Bit 3 - Underflow cumulative exception bit"]
182 #[inline(always)]
183 pub fn ufc(&mut self) -> UFC_W<3> {
184 UFC_W::new(self)
185 }
186 #[doc = "Bit 4 - Inexact cumulative exception bit"]
187 #[inline(always)]
188 pub fn ixc(&mut self) -> IXC_W<4> {
189 IXC_W::new(self)
190 }
191 #[doc = "Bit 7 - Input denormal cumulative exception bit."]
192 #[inline(always)]
193 pub fn idc(&mut self) -> IDC_W<7> {
194 IDC_W::new(self)
195 }
196 #[doc = "Bits 22:23 - Rounding Mode control field"]
197 #[inline(always)]
198 pub fn rmode(&mut self) -> RMODE_W<22> {
199 RMODE_W::new(self)
200 }
201 #[doc = "Bit 24 - Flush-to-zero mode control bit:"]
202 #[inline(always)]
203 pub fn fz(&mut self) -> FZ_W<24> {
204 FZ_W::new(self)
205 }
206 #[doc = "Bit 25 - Default NaN mode control bit"]
207 #[inline(always)]
208 pub fn dn(&mut self) -> DN_W<25> {
209 DN_W::new(self)
210 }
211 #[doc = "Bit 26 - Alternative half-precision control bit"]
212 #[inline(always)]
213 pub fn ahp(&mut self) -> AHP_W<26> {
214 AHP_W::new(self)
215 }
216 #[doc = "Bit 28 - Overflow condition code flag"]
217 #[inline(always)]
218 pub fn v(&mut self) -> V_W<28> {
219 V_W::new(self)
220 }
221 #[doc = "Bit 29 - Carry condition code flag"]
222 #[inline(always)]
223 pub fn c(&mut self) -> C_W<29> {
224 C_W::new(self)
225 }
226 #[doc = "Bit 30 - Zero condition code flag"]
227 #[inline(always)]
228 pub fn z(&mut self) -> Z_W<30> {
229 Z_W::new(self)
230 }
231 #[doc = "Bit 31 - Negative condition code flag"]
232 #[inline(always)]
233 pub fn n(&mut self) -> N_W<31> {
234 N_W::new(self)
235 }
236 #[doc = "Writes raw bits to the register."]
237 #[inline(always)]
238 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
239 self.0.bits(bits);
240 self
241 }
242}
243#[doc = "Floating-point status control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fpscr](index.html) module"]
244pub struct FPSCR_SPEC;
245impl crate::RegisterSpec for FPSCR_SPEC {
246 type Ux = u32;
247}
248#[doc = "`read()` method returns [fpscr::R](R) reader structure"]
249impl crate::Readable for FPSCR_SPEC {
250 type Reader = R;
251}
252#[doc = "`write(|w| ..)` method takes [fpscr::W](W) writer structure"]
253impl crate::Writable for FPSCR_SPEC {
254 type Writer = W;
255}
256#[doc = "`reset()` method sets FPSCR to value 0"]
257impl crate::Resettable for FPSCR_SPEC {
258 #[inline(always)]
259 fn reset_value() -> Self::Ux {
260 0
261 }
262}