Expand description
Field PLLSRC
writer - PLL entry clock source
Implementations
sourceimpl<'a, const O: u8> PLLSRC_W<'a, O>
impl<'a, const O: u8> PLLSRC_W<'a, O>
sourcepub fn hsi_div_prediv(self) -> &'a mut W
pub fn hsi_div_prediv(self) -> &'a mut W
HSI divided by PREDIV selected as PLL input clock
sourcepub fn hse_div_prediv(self) -> &'a mut W
pub fn hse_div_prediv(self) -> &'a mut W
HSE divided by PREDIV selected as PLL input clock