Enum stm32f3::stm32f373::tim6::cr1::URS_A [−][src]
pub enum URS_A { ANYEVENT, COUNTERONLY, }
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Update request source
Value on reset: 0
Variants
0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: Only counter overflow/underflow generates an update interrupt or DMA request