Enum stm32f3::stm32f373::tim3::ccmr1_output::OC1PE_A [−][src]
pub enum OC1PE_A { DISABLED, ENABLED, }
Expand description
Output compare 1 preload enable
Value on reset: 0
Variants
0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event