stm32f3_staging/stm32f373/
tsc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    ier: IER,
7    icr: ICR,
8    isr: ISR,
9    iohcr: IOHCR,
10    _reserved5: [u8; 0x04],
11    ioascr: IOASCR,
12    _reserved6: [u8; 0x04],
13    ioscr: IOSCR,
14    _reserved7: [u8; 0x04],
15    ioccr: IOCCR,
16    _reserved8: [u8; 0x04],
17    iogcsr: IOGCSR,
18    iogcr: [IOGCR; 8],
19}
20impl RegisterBlock {
21    ///0x00 - control register
22    #[inline(always)]
23    pub const fn cr(&self) -> &CR {
24        &self.cr
25    }
26    ///0x04 - interrupt enable register
27    #[inline(always)]
28    pub const fn ier(&self) -> &IER {
29        &self.ier
30    }
31    ///0x08 - interrupt clear register
32    #[inline(always)]
33    pub const fn icr(&self) -> &ICR {
34        &self.icr
35    }
36    ///0x0c - interrupt status register
37    #[inline(always)]
38    pub const fn isr(&self) -> &ISR {
39        &self.isr
40    }
41    ///0x10 - I/O hysteresis control register
42    #[inline(always)]
43    pub const fn iohcr(&self) -> &IOHCR {
44        &self.iohcr
45    }
46    ///0x18 - I/O analog switch control register
47    #[inline(always)]
48    pub const fn ioascr(&self) -> &IOASCR {
49        &self.ioascr
50    }
51    ///0x20 - I/O sampling control register
52    #[inline(always)]
53    pub const fn ioscr(&self) -> &IOSCR {
54        &self.ioscr
55    }
56    ///0x28 - I/O channel control register
57    #[inline(always)]
58    pub const fn ioccr(&self) -> &IOCCR {
59        &self.ioccr
60    }
61    ///0x30 - I/O group control status register
62    #[inline(always)]
63    pub const fn iogcsr(&self) -> &IOGCSR {
64        &self.iogcsr
65    }
66    ///0x34..0x54 - I/O group x counter register
67    ///
68    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `IOG1CR` register.</div>
69    #[inline(always)]
70    pub const fn iogcr(&self, n: usize) -> &IOGCR {
71        &self.iogcr[n]
72    }
73    ///Iterator for array of:
74    ///0x34..0x54 - I/O group x counter register
75    #[inline(always)]
76    pub fn iogcr_iter(&self) -> impl Iterator<Item = &IOGCR> {
77        self.iogcr.iter()
78    }
79    ///0x34 - I/O group x counter register
80    #[inline(always)]
81    pub const fn iog1cr(&self) -> &IOGCR {
82        self.iogcr(0)
83    }
84    ///0x38 - I/O group x counter register
85    #[inline(always)]
86    pub const fn iog2cr(&self) -> &IOGCR {
87        self.iogcr(1)
88    }
89    ///0x3c - I/O group x counter register
90    #[inline(always)]
91    pub const fn iog3cr(&self) -> &IOGCR {
92        self.iogcr(2)
93    }
94    ///0x40 - I/O group x counter register
95    #[inline(always)]
96    pub const fn iog4cr(&self) -> &IOGCR {
97        self.iogcr(3)
98    }
99    ///0x44 - I/O group x counter register
100    #[inline(always)]
101    pub const fn iog5cr(&self) -> &IOGCR {
102        self.iogcr(4)
103    }
104    ///0x48 - I/O group x counter register
105    #[inline(always)]
106    pub const fn iog6cr(&self) -> &IOGCR {
107        self.iogcr(5)
108    }
109    ///0x4c - I/O group x counter register
110    #[inline(always)]
111    pub const fn iog7cr(&self) -> &IOGCR {
112        self.iogcr(6)
113    }
114    ///0x50 - I/O group x counter register
115    #[inline(always)]
116    pub const fn iog8cr(&self) -> &IOGCR {
117        self.iogcr(7)
118    }
119}
120/**CR (rw) register accessor: control register
121
122You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:CR)
125
126For information about available fields see [`mod@cr`]
127module*/
128pub type CR = crate::Reg<cr::CRrs>;
129///control register
130pub mod cr;
131/**IER (rw) register accessor: interrupt enable register
132
133You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
134
135See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IER)
136
137For information about available fields see [`mod@ier`]
138module*/
139pub type IER = crate::Reg<ier::IERrs>;
140///interrupt enable register
141pub mod ier;
142/**ICR (rw) register accessor: interrupt clear register
143
144You can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
145
146See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:ICR)
147
148For information about available fields see [`mod@icr`]
149module*/
150pub type ICR = crate::Reg<icr::ICRrs>;
151///interrupt clear register
152pub mod icr;
153/**ISR (rw) register accessor: interrupt status register
154
155You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
156
157See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:ISR)
158
159For information about available fields see [`mod@isr`]
160module*/
161pub type ISR = crate::Reg<isr::ISRrs>;
162///interrupt status register
163pub mod isr;
164/**IOHCR (rw) register accessor: I/O hysteresis control register
165
166You can [`read`](crate::Reg::read) this register and get [`iohcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iohcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOHCR)
169
170For information about available fields see [`mod@iohcr`]
171module*/
172pub type IOHCR = crate::Reg<iohcr::IOHCRrs>;
173///I/O hysteresis control register
174pub mod iohcr;
175/**IOASCR (rw) register accessor: I/O analog switch control register
176
177You can [`read`](crate::Reg::read) this register and get [`ioascr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioascr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
178
179See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOASCR)
180
181For information about available fields see [`mod@ioascr`]
182module*/
183pub type IOASCR = crate::Reg<ioascr::IOASCRrs>;
184///I/O analog switch control register
185pub mod ioascr;
186/**IOSCR (rw) register accessor: I/O sampling control register
187
188You can [`read`](crate::Reg::read) this register and get [`ioscr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioscr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOSCR)
191
192For information about available fields see [`mod@ioscr`]
193module*/
194pub type IOSCR = crate::Reg<ioscr::IOSCRrs>;
195///I/O sampling control register
196pub mod ioscr;
197/**IOCCR (rw) register accessor: I/O channel control register
198
199You can [`read`](crate::Reg::read) this register and get [`ioccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOCCR)
202
203For information about available fields see [`mod@ioccr`]
204module*/
205pub type IOCCR = crate::Reg<ioccr::IOCCRrs>;
206///I/O channel control register
207pub mod ioccr;
208/**IOGCSR (rw) register accessor: I/O group control status register
209
210You can [`read`](crate::Reg::read) this register and get [`iogcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iogcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOGCSR)
213
214For information about available fields see [`mod@iogcsr`]
215module*/
216pub type IOGCSR = crate::Reg<iogcsr::IOGCSRrs>;
217///I/O group control status register
218pub mod iogcsr;
219/**IOGCR (r) register accessor: I/O group x counter register
220
221You can [`read`](crate::Reg::read) this register and get [`iogcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOG[1]CR)
224
225For information about available fields see [`mod@iogcr`]
226module*/
227pub type IOGCR = crate::Reg<iogcr::IOGCRrs>;
228///I/O group x counter register
229pub mod iogcr;
stm32f3_staging/stm32f373/tsc.rs

stm32f3_staging/stm32f373/
tsc.rs
