stm32f3_staging/stm32f373/tim2/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-4)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-4)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-4)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-4)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117///Field `CCNP(1-4)` reader - Capture/Compare %s output Polarity
118pub type CCNP_R = crate::BitReader;
119///Field `CCNP(1-4)` writer - Capture/Compare %s output Polarity
120pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG>;
121impl R {
122    ///Capture/Compare (1-4) output enable
123    ///
124    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
125    #[inline(always)]
126    pub fn cce(&self, n: u8) -> CCE_R {
127        #[allow(clippy::no_effect)] [(); 4][n as usize];
128        CCE_R::new(((self.bits >> (n * 4)) & 1) != 0)
129    }
130    ///Iterator for array of:
131    ///Capture/Compare (1-4) output enable
132    #[inline(always)]
133    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
134        (0..4).map(move |n| CCE_R::new(((self.bits >> (n * 4)) & 1) != 0))
135    }
136    ///Bit 0 - Capture/Compare 1 output enable
137    #[inline(always)]
138    pub fn cc1e(&self) -> CCE_R {
139        CCE_R::new((self.bits & 1) != 0)
140    }
141    ///Bit 4 - Capture/Compare 2 output enable
142    #[inline(always)]
143    pub fn cc2e(&self) -> CCE_R {
144        CCE_R::new(((self.bits >> 4) & 1) != 0)
145    }
146    ///Bit 8 - Capture/Compare 3 output enable
147    #[inline(always)]
148    pub fn cc3e(&self) -> CCE_R {
149        CCE_R::new(((self.bits >> 8) & 1) != 0)
150    }
151    ///Bit 12 - Capture/Compare 4 output enable
152    #[inline(always)]
153    pub fn cc4e(&self) -> CCE_R {
154        CCE_R::new(((self.bits >> 12) & 1) != 0)
155    }
156    ///Capture/Compare (1-4) output Polarity
157    ///
158    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
159    #[inline(always)]
160    pub fn ccp(&self, n: u8) -> CCP_R {
161        #[allow(clippy::no_effect)] [(); 4][n as usize];
162        CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
163    }
164    ///Iterator for array of:
165    ///Capture/Compare (1-4) output Polarity
166    #[inline(always)]
167    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
168        (0..4).map(move |n| CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
169    }
170    ///Bit 1 - Capture/Compare 1 output Polarity
171    #[inline(always)]
172    pub fn cc1p(&self) -> CCP_R {
173        CCP_R::new(((self.bits >> 1) & 1) != 0)
174    }
175    ///Bit 5 - Capture/Compare 2 output Polarity
176    #[inline(always)]
177    pub fn cc2p(&self) -> CCP_R {
178        CCP_R::new(((self.bits >> 5) & 1) != 0)
179    }
180    ///Bit 9 - Capture/Compare 3 output Polarity
181    #[inline(always)]
182    pub fn cc3p(&self) -> CCP_R {
183        CCP_R::new(((self.bits >> 9) & 1) != 0)
184    }
185    ///Bit 13 - Capture/Compare 4 output Polarity
186    #[inline(always)]
187    pub fn cc4p(&self) -> CCP_R {
188        CCP_R::new(((self.bits >> 13) & 1) != 0)
189    }
190    ///Capture/Compare (1-4) output Polarity
191    ///
192    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
193    #[inline(always)]
194    pub fn ccnp(&self, n: u8) -> CCNP_R {
195        #[allow(clippy::no_effect)] [(); 4][n as usize];
196        CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
197    }
198    ///Iterator for array of:
199    ///Capture/Compare (1-4) output Polarity
200    #[inline(always)]
201    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
202        (0..4).map(move |n| CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
203    }
204    ///Bit 3 - Capture/Compare 1 output Polarity
205    #[inline(always)]
206    pub fn cc1np(&self) -> CCNP_R {
207        CCNP_R::new(((self.bits >> 3) & 1) != 0)
208    }
209    ///Bit 7 - Capture/Compare 2 output Polarity
210    #[inline(always)]
211    pub fn cc2np(&self) -> CCNP_R {
212        CCNP_R::new(((self.bits >> 7) & 1) != 0)
213    }
214    ///Bit 11 - Capture/Compare 3 output Polarity
215    #[inline(always)]
216    pub fn cc3np(&self) -> CCNP_R {
217        CCNP_R::new(((self.bits >> 11) & 1) != 0)
218    }
219    ///Bit 15 - Capture/Compare 4 output Polarity
220    #[inline(always)]
221    pub fn cc4np(&self) -> CCNP_R {
222        CCNP_R::new(((self.bits >> 15) & 1) != 0)
223    }
224}
225impl core::fmt::Debug for R {
226    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
227        f.debug_struct("CCER")
228            .field("cc1e", &self.cc1e())
229            .field("cc2e", &self.cc2e())
230            .field("cc3e", &self.cc3e())
231            .field("cc4e", &self.cc4e())
232            .field("cc1p", &self.cc1p())
233            .field("cc2p", &self.cc2p())
234            .field("cc3p", &self.cc3p())
235            .field("cc4p", &self.cc4p())
236            .field("cc1np", &self.cc1np())
237            .field("cc2np", &self.cc2np())
238            .field("cc3np", &self.cc3np())
239            .field("cc4np", &self.cc4np())
240            .finish()
241    }
242}
243impl W {
244    ///Capture/Compare (1-4) output enable
245    ///
246    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
247    #[inline(always)]
248    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
249        #[allow(clippy::no_effect)] [(); 4][n as usize];
250        CCE_W::new(self, n * 4)
251    }
252    ///Bit 0 - Capture/Compare 1 output enable
253    #[inline(always)]
254    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
255        CCE_W::new(self, 0)
256    }
257    ///Bit 4 - Capture/Compare 2 output enable
258    #[inline(always)]
259    pub fn cc2e(&mut self) -> CCE_W<CCERrs> {
260        CCE_W::new(self, 4)
261    }
262    ///Bit 8 - Capture/Compare 3 output enable
263    #[inline(always)]
264    pub fn cc3e(&mut self) -> CCE_W<CCERrs> {
265        CCE_W::new(self, 8)
266    }
267    ///Bit 12 - Capture/Compare 4 output enable
268    #[inline(always)]
269    pub fn cc4e(&mut self) -> CCE_W<CCERrs> {
270        CCE_W::new(self, 12)
271    }
272    ///Capture/Compare (1-4) output Polarity
273    ///
274    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
275    #[inline(always)]
276    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
277        #[allow(clippy::no_effect)] [(); 4][n as usize];
278        CCP_W::new(self, n * 4 + 1)
279    }
280    ///Bit 1 - Capture/Compare 1 output Polarity
281    #[inline(always)]
282    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
283        CCP_W::new(self, 1)
284    }
285    ///Bit 5 - Capture/Compare 2 output Polarity
286    #[inline(always)]
287    pub fn cc2p(&mut self) -> CCP_W<CCERrs> {
288        CCP_W::new(self, 5)
289    }
290    ///Bit 9 - Capture/Compare 3 output Polarity
291    #[inline(always)]
292    pub fn cc3p(&mut self) -> CCP_W<CCERrs> {
293        CCP_W::new(self, 9)
294    }
295    ///Bit 13 - Capture/Compare 4 output Polarity
296    #[inline(always)]
297    pub fn cc4p(&mut self) -> CCP_W<CCERrs> {
298        CCP_W::new(self, 13)
299    }
300    ///Capture/Compare (1-4) output Polarity
301    ///
302    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
303    #[inline(always)]
304    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
305        #[allow(clippy::no_effect)] [(); 4][n as usize];
306        CCNP_W::new(self, n * 4 + 3)
307    }
308    ///Bit 3 - Capture/Compare 1 output Polarity
309    #[inline(always)]
310    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
311        CCNP_W::new(self, 3)
312    }
313    ///Bit 7 - Capture/Compare 2 output Polarity
314    #[inline(always)]
315    pub fn cc2np(&mut self) -> CCNP_W<CCERrs> {
316        CCNP_W::new(self, 7)
317    }
318    ///Bit 11 - Capture/Compare 3 output Polarity
319    #[inline(always)]
320    pub fn cc3np(&mut self) -> CCNP_W<CCERrs> {
321        CCNP_W::new(self, 11)
322    }
323    ///Bit 15 - Capture/Compare 4 output Polarity
324    #[inline(always)]
325    pub fn cc4np(&mut self) -> CCNP_W<CCERrs> {
326        CCNP_W::new(self, 15)
327    }
328}
329/**capture/compare enable register
330
331You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
332
333See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCER)*/
334pub struct CCERrs;
335impl crate::RegisterSpec for CCERrs {
336    type Ux = u32;
337}
338///`read()` method returns [`ccer::R`](R) reader structure
339impl crate::Readable for CCERrs {}
340///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
341impl crate::Writable for CCERrs {
342    type Safety = crate::Unsafe;
343    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
344    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
345}
346///`reset()` method sets CCER to value 0
347impl crate::Resettable for CCERrs {
348    const RESET_VALUE: u32 = 0;
349}
stm32f3_staging/stm32f373/tim2/ccer.rs

stm32f3_staging/stm32f373/tim2/
ccer.rs
