stm32f3_staging/stm32f373/
tim2.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved12: [u8; 0x04],
18    ccr: [CCR; 4],
19    _reserved13: [u8; 0x04],
20    dcr: DCR,
21    dmar: DMAR,
22    or: OR,
23}
24impl RegisterBlock {
25    ///0x00 - control register 1
26    #[inline(always)]
27    pub const fn cr1(&self) -> &CR1 {
28        &self.cr1
29    }
30    ///0x04 - control register 2
31    #[inline(always)]
32    pub const fn cr2(&self) -> &CR2 {
33        &self.cr2
34    }
35    ///0x08 - slave mode control register
36    #[inline(always)]
37    pub const fn smcr(&self) -> &SMCR {
38        &self.smcr
39    }
40    ///0x0c - DMA/Interrupt enable register
41    #[inline(always)]
42    pub const fn dier(&self) -> &DIER {
43        &self.dier
44    }
45    ///0x10 - status register
46    #[inline(always)]
47    pub const fn sr(&self) -> &SR {
48        &self.sr
49    }
50    ///0x14 - event generation register
51    #[inline(always)]
52    pub const fn egr(&self) -> &EGR {
53        &self.egr
54    }
55    ///0x18 - capture/compare mode register 1 (input mode)
56    #[inline(always)]
57    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
58        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
59    }
60    ///0x18 - capture/compare mode register 1 (output mode)
61    #[inline(always)]
62    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
64    }
65    ///0x1c - capture/compare mode register 2 (input mode)
66    #[inline(always)]
67    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
68        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
69    }
70    ///0x1c - capture/compare mode register 2 (output mode)
71    #[inline(always)]
72    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
73        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
74    }
75    ///0x20 - capture/compare enable register
76    #[inline(always)]
77    pub const fn ccer(&self) -> &CCER {
78        &self.ccer
79    }
80    ///0x24 - counter
81    #[inline(always)]
82    pub const fn cnt(&self) -> &CNT {
83        &self.cnt
84    }
85    ///0x28 - prescaler
86    #[inline(always)]
87    pub const fn psc(&self) -> &PSC {
88        &self.psc
89    }
90    ///0x2c - auto-reload register
91    #[inline(always)]
92    pub const fn arr(&self) -> &ARR {
93        &self.arr
94    }
95    ///0x34..0x44 - capture/compare register
96    ///
97    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
98    #[inline(always)]
99    pub const fn ccr(&self, n: usize) -> &CCR {
100        &self.ccr[n]
101    }
102    ///Iterator for array of:
103    ///0x34..0x44 - capture/compare register
104    #[inline(always)]
105    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
106        self.ccr.iter()
107    }
108    ///0x34 - capture/compare register
109    #[inline(always)]
110    pub const fn ccr1(&self) -> &CCR {
111        self.ccr(0)
112    }
113    ///0x38 - capture/compare register
114    #[inline(always)]
115    pub const fn ccr2(&self) -> &CCR {
116        self.ccr(1)
117    }
118    ///0x3c - capture/compare register
119    #[inline(always)]
120    pub const fn ccr3(&self) -> &CCR {
121        self.ccr(2)
122    }
123    ///0x40 - capture/compare register
124    #[inline(always)]
125    pub const fn ccr4(&self) -> &CCR {
126        self.ccr(3)
127    }
128    ///0x48 - DMA control register
129    #[inline(always)]
130    pub const fn dcr(&self) -> &DCR {
131        &self.dcr
132    }
133    ///0x4c - DMA address for full transfer
134    #[inline(always)]
135    pub const fn dmar(&self) -> &DMAR {
136        &self.dmar
137    }
138    ///0x50 - option register
139    #[inline(always)]
140    pub const fn or(&self) -> &OR {
141        &self.or
142    }
143}
144/**CR1 (rw) register accessor: control register 1
145
146You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
147
148See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CR1)
149
150For information about available fields see [`mod@cr1`]
151module*/
152pub type CR1 = crate::Reg<cr1::CR1rs>;
153///control register 1
154pub mod cr1;
155/**CR2 (rw) register accessor: control register 2
156
157You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
158
159See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CR2)
160
161For information about available fields see [`mod@cr2`]
162module*/
163pub type CR2 = crate::Reg<cr2::CR2rs>;
164///control register 2
165pub mod cr2;
166/**SMCR (rw) register accessor: slave mode control register
167
168You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
169
170See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:SMCR)
171
172For information about available fields see [`mod@smcr`]
173module*/
174pub type SMCR = crate::Reg<smcr::SMCRrs>;
175///slave mode control register
176pub mod smcr;
177/**DIER (rw) register accessor: DMA/Interrupt enable register
178
179You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
180
181See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:DIER)
182
183For information about available fields see [`mod@dier`]
184module*/
185pub type DIER = crate::Reg<dier::DIERrs>;
186///DMA/Interrupt enable register
187pub mod dier;
188/**SR (rw) register accessor: status register
189
190You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
191
192See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:SR)
193
194For information about available fields see [`mod@sr`]
195module*/
196pub type SR = crate::Reg<sr::SRrs>;
197///status register
198pub mod sr;
199/**EGR (w) register accessor: event generation register
200
201You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
202
203See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:EGR)
204
205For information about available fields see [`mod@egr`]
206module*/
207pub type EGR = crate::Reg<egr::EGRrs>;
208///event generation register
209pub mod egr;
210/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
211
212You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCMR1_Output)
215
216For information about available fields see [`mod@ccmr1_output`]
217module*/
218#[doc(alias = "CCMR1_Output")]
219pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
220///capture/compare mode register 1 (output mode)
221pub mod ccmr1_output;
222/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
223
224You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
225
226See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCMR1_Input)
227
228For information about available fields see [`mod@ccmr1_input`]
229module*/
230#[doc(alias = "CCMR1_Input")]
231pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
232///capture/compare mode register 1 (input mode)
233pub mod ccmr1_input;
234/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
235
236You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
237
238See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCMR2_Output)
239
240For information about available fields see [`mod@ccmr2_output`]
241module*/
242#[doc(alias = "CCMR2_Output")]
243pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
244///capture/compare mode register 2 (output mode)
245pub mod ccmr2_output;
246/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
247
248You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
249
250See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCMR2_Input)
251
252For information about available fields see [`mod@ccmr2_input`]
253module*/
254#[doc(alias = "CCMR2_Input")]
255pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
256///capture/compare mode register 2 (input mode)
257pub mod ccmr2_input;
258/**CCER (rw) register accessor: capture/compare enable register
259
260You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
261
262See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCER)
263
264For information about available fields see [`mod@ccer`]
265module*/
266pub type CCER = crate::Reg<ccer::CCERrs>;
267///capture/compare enable register
268pub mod ccer;
269/**CNT (rw) register accessor: counter
270
271You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
272
273See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CNT)
274
275For information about available fields see [`mod@cnt`]
276module*/
277pub type CNT = crate::Reg<cnt::CNTrs>;
278///counter
279pub mod cnt;
280/**PSC (rw) register accessor: prescaler
281
282You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
283
284See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:PSC)
285
286For information about available fields see [`mod@psc`]
287module*/
288pub type PSC = crate::Reg<psc::PSCrs>;
289///prescaler
290pub mod psc;
291/**ARR (rw) register accessor: auto-reload register
292
293You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
294
295See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:ARR)
296
297For information about available fields see [`mod@arr`]
298module*/
299pub type ARR = crate::Reg<arr::ARRrs>;
300///auto-reload register
301pub mod arr;
302/**CCR (rw) register accessor: capture/compare register
303
304You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
305
306See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:CCR[1])
307
308For information about available fields see [`mod@ccr`]
309module*/
310pub type CCR = crate::Reg<ccr::CCRrs>;
311///capture/compare register
312pub mod ccr;
313/**DCR (rw) register accessor: DMA control register
314
315You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
316
317See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:DCR)
318
319For information about available fields see [`mod@dcr`]
320module*/
321pub type DCR = crate::Reg<dcr::DCRrs>;
322///DMA control register
323pub mod dcr;
324/**DMAR (rw) register accessor: DMA address for full transfer
325
326You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
327
328See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:DMAR)
329
330For information about available fields see [`mod@dmar`]
331module*/
332pub type DMAR = crate::Reg<dmar::DMARrs>;
333///DMA address for full transfer
334pub mod dmar;
335/**OR (rw) register accessor: option register
336
337You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
338
339See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM2:OR)
340
341For information about available fields see [`mod@or`]
342module*/
343pub type OR = crate::Reg<or::ORrs>;
344///option register
345pub mod or;
stm32f3_staging/stm32f373/tim2.rs

stm32f3_staging/stm32f373/
tim2.rs
