stm32f3_staging/stm32f373/
rcc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    cfgr: CFGR,
7    cir: CIR,
8    apb2rstr: APB2RSTR,
9    apb1rstr: APB1RSTR,
10    ahbenr: AHBENR,
11    apb2enr: APB2ENR,
12    apb1enr: APB1ENR,
13    bdcr: BDCR,
14    csr: CSR,
15    ahbrstr: AHBRSTR,
16    cfgr2: CFGR2,
17    cfgr3: CFGR3,
18}
19impl RegisterBlock {
20    ///0x00 - Clock control register
21    #[inline(always)]
22    pub const fn cr(&self) -> &CR {
23        &self.cr
24    }
25    ///0x04 - Clock configuration register (RCC_CFGR)
26    #[inline(always)]
27    pub const fn cfgr(&self) -> &CFGR {
28        &self.cfgr
29    }
30    ///0x08 - Clock interrupt register (RCC_CIR)
31    #[inline(always)]
32    pub const fn cir(&self) -> &CIR {
33        &self.cir
34    }
35    ///0x0c - APB2 peripheral reset register (RCC_APB2RSTR)
36    #[inline(always)]
37    pub const fn apb2rstr(&self) -> &APB2RSTR {
38        &self.apb2rstr
39    }
40    ///0x10 - APB1 peripheral reset register (RCC_APB1RSTR)
41    #[inline(always)]
42    pub const fn apb1rstr(&self) -> &APB1RSTR {
43        &self.apb1rstr
44    }
45    ///0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)
46    #[inline(always)]
47    pub const fn ahbenr(&self) -> &AHBENR {
48        &self.ahbenr
49    }
50    ///0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)
51    #[inline(always)]
52    pub const fn apb2enr(&self) -> &APB2ENR {
53        &self.apb2enr
54    }
55    ///0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)
56    #[inline(always)]
57    pub const fn apb1enr(&self) -> &APB1ENR {
58        &self.apb1enr
59    }
60    ///0x20 - Backup domain control register (RCC_BDCR)
61    #[inline(always)]
62    pub const fn bdcr(&self) -> &BDCR {
63        &self.bdcr
64    }
65    ///0x24 - Control/status register (RCC_CSR)
66    #[inline(always)]
67    pub const fn csr(&self) -> &CSR {
68        &self.csr
69    }
70    ///0x28 - AHB peripheral reset register
71    #[inline(always)]
72    pub const fn ahbrstr(&self) -> &AHBRSTR {
73        &self.ahbrstr
74    }
75    ///0x2c - Clock configuration register 2
76    #[inline(always)]
77    pub const fn cfgr2(&self) -> &CFGR2 {
78        &self.cfgr2
79    }
80    ///0x30 - Clock configuration register 3
81    #[inline(always)]
82    pub const fn cfgr3(&self) -> &CFGR3 {
83        &self.cfgr3
84    }
85}
86/**CR (rw) register accessor: Clock control register
87
88You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:CR)
91
92For information about available fields see [`mod@cr`]
93module*/
94pub type CR = crate::Reg<cr::CRrs>;
95///Clock control register
96pub mod cr;
97/**CFGR (rw) register accessor: Clock configuration register (RCC_CFGR)
98
99You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:CFGR)
102
103For information about available fields see [`mod@cfgr`]
104module*/
105pub type CFGR = crate::Reg<cfgr::CFGRrs>;
106///Clock configuration register (RCC_CFGR)
107pub mod cfgr;
108/**CIR (rw) register accessor: Clock interrupt register (RCC_CIR)
109
110You can [`read`](crate::Reg::read) this register and get [`cir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:CIR)
113
114For information about available fields see [`mod@cir`]
115module*/
116pub type CIR = crate::Reg<cir::CIRrs>;
117///Clock interrupt register (RCC_CIR)
118pub mod cir;
119/**APB2RSTR (rw) register accessor: APB2 peripheral reset register (RCC_APB2RSTR)
120
121You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
122
123See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:APB2RSTR)
124
125For information about available fields see [`mod@apb2rstr`]
126module*/
127pub type APB2RSTR = crate::Reg<apb2rstr::APB2RSTRrs>;
128///APB2 peripheral reset register (RCC_APB2RSTR)
129pub mod apb2rstr;
130/**APB1RSTR (rw) register accessor: APB1 peripheral reset register (RCC_APB1RSTR)
131
132You can [`read`](crate::Reg::read) this register and get [`apb1rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:APB1RSTR)
135
136For information about available fields see [`mod@apb1rstr`]
137module*/
138pub type APB1RSTR = crate::Reg<apb1rstr::APB1RSTRrs>;
139///APB1 peripheral reset register (RCC_APB1RSTR)
140pub mod apb1rstr;
141/**AHBENR (rw) register accessor: AHB Peripheral Clock enable register (RCC_AHBENR)
142
143You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
144
145See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:AHBENR)
146
147For information about available fields see [`mod@ahbenr`]
148module*/
149pub type AHBENR = crate::Reg<ahbenr::AHBENRrs>;
150///AHB Peripheral Clock enable register (RCC_AHBENR)
151pub mod ahbenr;
152/**APB2ENR (rw) register accessor: APB2 peripheral clock enable register (RCC_APB2ENR)
153
154You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
155
156See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:APB2ENR)
157
158For information about available fields see [`mod@apb2enr`]
159module*/
160pub type APB2ENR = crate::Reg<apb2enr::APB2ENRrs>;
161///APB2 peripheral clock enable register (RCC_APB2ENR)
162pub mod apb2enr;
163/**APB1ENR (rw) register accessor: APB1 peripheral clock enable register (RCC_APB1ENR)
164
165You can [`read`](crate::Reg::read) this register and get [`apb1enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
166
167See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:APB1ENR)
168
169For information about available fields see [`mod@apb1enr`]
170module*/
171pub type APB1ENR = crate::Reg<apb1enr::APB1ENRrs>;
172///APB1 peripheral clock enable register (RCC_APB1ENR)
173pub mod apb1enr;
174/**BDCR (rw) register accessor: Backup domain control register (RCC_BDCR)
175
176You can [`read`](crate::Reg::read) this register and get [`bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:BDCR)
179
180For information about available fields see [`mod@bdcr`]
181module*/
182pub type BDCR = crate::Reg<bdcr::BDCRrs>;
183///Backup domain control register (RCC_BDCR)
184pub mod bdcr;
185/**CSR (rw) register accessor: Control/status register (RCC_CSR)
186
187You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
188
189See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:CSR)
190
191For information about available fields see [`mod@csr`]
192module*/
193pub type CSR = crate::Reg<csr::CSRrs>;
194///Control/status register (RCC_CSR)
195pub mod csr;
196/**AHBRSTR (rw) register accessor: AHB peripheral reset register
197
198You can [`read`](crate::Reg::read) this register and get [`ahbrstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbrstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
199
200See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:AHBRSTR)
201
202For information about available fields see [`mod@ahbrstr`]
203module*/
204pub type AHBRSTR = crate::Reg<ahbrstr::AHBRSTRrs>;
205///AHB peripheral reset register
206pub mod ahbrstr;
207/**CFGR2 (rw) register accessor: Clock configuration register 2
208
209You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:CFGR2)
212
213For information about available fields see [`mod@cfgr2`]
214module*/
215pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
216///Clock configuration register 2
217pub mod cfgr2;
218/**CFGR3 (rw) register accessor: Clock configuration register 3
219
220You can [`read`](crate::Reg::read) this register and get [`cfgr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#RCC:CFGR3)
223
224For information about available fields see [`mod@cfgr3`]
225module*/
226pub type CFGR3 = crate::Reg<cfgr3::CFGR3rs>;
227///Clock configuration register 3
228pub mod cfgr3;
stm32f3_staging/stm32f373/rcc.rs

stm32f3_staging/stm32f373/
rcc.rs
