stm32f3_staging/stm32f373/gpioc/
ospeedr.rs

1///Register `OSPEEDR` reader
2pub type R = crate::R<OSPEEDRrs>;
3///Register `OSPEEDR` writer
4pub type W = crate::W<OSPEEDRrs>;
5/**Port x configuration pin %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum OSPEEDR0 {
12    ///0: Low speed
13    LowSpeed = 0,
14    ///1: Medium speed
15    MediumSpeed = 1,
16    ///3: High speed
17    HighSpeed = 3,
18}
19impl From<OSPEEDR0> for u8 {
20    #[inline(always)]
21    fn from(variant: OSPEEDR0) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for OSPEEDR0 {
26    type Ux = u8;
27}
28impl crate::IsEnum for OSPEEDR0 {}
29///Field `OSPEEDR(0-15)` reader - Port x configuration pin %s
30pub type OSPEEDR_R = crate::FieldReader<OSPEEDR0>;
31impl OSPEEDR_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<OSPEEDR0> {
35        match self.bits {
36            0 => Some(OSPEEDR0::LowSpeed),
37            1 => Some(OSPEEDR0::MediumSpeed),
38            3 => Some(OSPEEDR0::HighSpeed),
39            _ => None,
40        }
41    }
42    ///Low speed
43    #[inline(always)]
44    pub fn is_low_speed(&self) -> bool {
45        *self == OSPEEDR0::LowSpeed
46    }
47    ///Medium speed
48    #[inline(always)]
49    pub fn is_medium_speed(&self) -> bool {
50        *self == OSPEEDR0::MediumSpeed
51    }
52    ///High speed
53    #[inline(always)]
54    pub fn is_high_speed(&self) -> bool {
55        *self == OSPEEDR0::HighSpeed
56    }
57}
58///Field `OSPEEDR(0-15)` writer - Port x configuration pin %s
59pub type OSPEEDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OSPEEDR0>;
60impl<'a, REG> OSPEEDR_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///Low speed
66    #[inline(always)]
67    pub fn low_speed(self) -> &'a mut crate::W<REG> {
68        self.variant(OSPEEDR0::LowSpeed)
69    }
70    ///Medium speed
71    #[inline(always)]
72    pub fn medium_speed(self) -> &'a mut crate::W<REG> {
73        self.variant(OSPEEDR0::MediumSpeed)
74    }
75    ///High speed
76    #[inline(always)]
77    pub fn high_speed(self) -> &'a mut crate::W<REG> {
78        self.variant(OSPEEDR0::HighSpeed)
79    }
80}
81impl R {
82    ///Port x configuration pin (0-15)
83    ///
84    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
85    #[inline(always)]
86    pub fn ospeedr(&self, n: u8) -> OSPEEDR_R {
87        #[allow(clippy::no_effect)] [(); 16][n as usize];
88        OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8)
89    }
90    ///Iterator for array of:
91    ///Port x configuration pin (0-15)
92    #[inline(always)]
93    pub fn ospeedr_iter(&self) -> impl Iterator<Item = OSPEEDR_R> + '_ {
94        (0..16).map(move |n| OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8))
95    }
96    ///Bits 0:1 - Port x configuration pin 0
97    #[inline(always)]
98    pub fn ospeedr0(&self) -> OSPEEDR_R {
99        OSPEEDR_R::new((self.bits & 3) as u8)
100    }
101    ///Bits 2:3 - Port x configuration pin 1
102    #[inline(always)]
103    pub fn ospeedr1(&self) -> OSPEEDR_R {
104        OSPEEDR_R::new(((self.bits >> 2) & 3) as u8)
105    }
106    ///Bits 4:5 - Port x configuration pin 2
107    #[inline(always)]
108    pub fn ospeedr2(&self) -> OSPEEDR_R {
109        OSPEEDR_R::new(((self.bits >> 4) & 3) as u8)
110    }
111    ///Bits 6:7 - Port x configuration pin 3
112    #[inline(always)]
113    pub fn ospeedr3(&self) -> OSPEEDR_R {
114        OSPEEDR_R::new(((self.bits >> 6) & 3) as u8)
115    }
116    ///Bits 8:9 - Port x configuration pin 4
117    #[inline(always)]
118    pub fn ospeedr4(&self) -> OSPEEDR_R {
119        OSPEEDR_R::new(((self.bits >> 8) & 3) as u8)
120    }
121    ///Bits 10:11 - Port x configuration pin 5
122    #[inline(always)]
123    pub fn ospeedr5(&self) -> OSPEEDR_R {
124        OSPEEDR_R::new(((self.bits >> 10) & 3) as u8)
125    }
126    ///Bits 12:13 - Port x configuration pin 6
127    #[inline(always)]
128    pub fn ospeedr6(&self) -> OSPEEDR_R {
129        OSPEEDR_R::new(((self.bits >> 12) & 3) as u8)
130    }
131    ///Bits 14:15 - Port x configuration pin 7
132    #[inline(always)]
133    pub fn ospeedr7(&self) -> OSPEEDR_R {
134        OSPEEDR_R::new(((self.bits >> 14) & 3) as u8)
135    }
136    ///Bits 16:17 - Port x configuration pin 8
137    #[inline(always)]
138    pub fn ospeedr8(&self) -> OSPEEDR_R {
139        OSPEEDR_R::new(((self.bits >> 16) & 3) as u8)
140    }
141    ///Bits 18:19 - Port x configuration pin 9
142    #[inline(always)]
143    pub fn ospeedr9(&self) -> OSPEEDR_R {
144        OSPEEDR_R::new(((self.bits >> 18) & 3) as u8)
145    }
146    ///Bits 20:21 - Port x configuration pin 10
147    #[inline(always)]
148    pub fn ospeedr10(&self) -> OSPEEDR_R {
149        OSPEEDR_R::new(((self.bits >> 20) & 3) as u8)
150    }
151    ///Bits 22:23 - Port x configuration pin 11
152    #[inline(always)]
153    pub fn ospeedr11(&self) -> OSPEEDR_R {
154        OSPEEDR_R::new(((self.bits >> 22) & 3) as u8)
155    }
156    ///Bits 24:25 - Port x configuration pin 12
157    #[inline(always)]
158    pub fn ospeedr12(&self) -> OSPEEDR_R {
159        OSPEEDR_R::new(((self.bits >> 24) & 3) as u8)
160    }
161    ///Bits 26:27 - Port x configuration pin 13
162    #[inline(always)]
163    pub fn ospeedr13(&self) -> OSPEEDR_R {
164        OSPEEDR_R::new(((self.bits >> 26) & 3) as u8)
165    }
166    ///Bits 28:29 - Port x configuration pin 14
167    #[inline(always)]
168    pub fn ospeedr14(&self) -> OSPEEDR_R {
169        OSPEEDR_R::new(((self.bits >> 28) & 3) as u8)
170    }
171    ///Bits 30:31 - Port x configuration pin 15
172    #[inline(always)]
173    pub fn ospeedr15(&self) -> OSPEEDR_R {
174        OSPEEDR_R::new(((self.bits >> 30) & 3) as u8)
175    }
176}
177impl core::fmt::Debug for R {
178    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
179        f.debug_struct("OSPEEDR")
180            .field("ospeedr0", &self.ospeedr0())
181            .field("ospeedr1", &self.ospeedr1())
182            .field("ospeedr2", &self.ospeedr2())
183            .field("ospeedr3", &self.ospeedr3())
184            .field("ospeedr4", &self.ospeedr4())
185            .field("ospeedr5", &self.ospeedr5())
186            .field("ospeedr6", &self.ospeedr6())
187            .field("ospeedr7", &self.ospeedr7())
188            .field("ospeedr8", &self.ospeedr8())
189            .field("ospeedr9", &self.ospeedr9())
190            .field("ospeedr10", &self.ospeedr10())
191            .field("ospeedr11", &self.ospeedr11())
192            .field("ospeedr12", &self.ospeedr12())
193            .field("ospeedr13", &self.ospeedr13())
194            .field("ospeedr14", &self.ospeedr14())
195            .field("ospeedr15", &self.ospeedr15())
196            .finish()
197    }
198}
199impl W {
200    ///Port x configuration pin (0-15)
201    ///
202    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
203    #[inline(always)]
204    pub fn ospeedr(&mut self, n: u8) -> OSPEEDR_W<OSPEEDRrs> {
205        #[allow(clippy::no_effect)] [(); 16][n as usize];
206        OSPEEDR_W::new(self, n * 2)
207    }
208    ///Bits 0:1 - Port x configuration pin 0
209    #[inline(always)]
210    pub fn ospeedr0(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
211        OSPEEDR_W::new(self, 0)
212    }
213    ///Bits 2:3 - Port x configuration pin 1
214    #[inline(always)]
215    pub fn ospeedr1(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
216        OSPEEDR_W::new(self, 2)
217    }
218    ///Bits 4:5 - Port x configuration pin 2
219    #[inline(always)]
220    pub fn ospeedr2(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
221        OSPEEDR_W::new(self, 4)
222    }
223    ///Bits 6:7 - Port x configuration pin 3
224    #[inline(always)]
225    pub fn ospeedr3(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
226        OSPEEDR_W::new(self, 6)
227    }
228    ///Bits 8:9 - Port x configuration pin 4
229    #[inline(always)]
230    pub fn ospeedr4(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
231        OSPEEDR_W::new(self, 8)
232    }
233    ///Bits 10:11 - Port x configuration pin 5
234    #[inline(always)]
235    pub fn ospeedr5(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
236        OSPEEDR_W::new(self, 10)
237    }
238    ///Bits 12:13 - Port x configuration pin 6
239    #[inline(always)]
240    pub fn ospeedr6(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
241        OSPEEDR_W::new(self, 12)
242    }
243    ///Bits 14:15 - Port x configuration pin 7
244    #[inline(always)]
245    pub fn ospeedr7(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
246        OSPEEDR_W::new(self, 14)
247    }
248    ///Bits 16:17 - Port x configuration pin 8
249    #[inline(always)]
250    pub fn ospeedr8(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
251        OSPEEDR_W::new(self, 16)
252    }
253    ///Bits 18:19 - Port x configuration pin 9
254    #[inline(always)]
255    pub fn ospeedr9(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
256        OSPEEDR_W::new(self, 18)
257    }
258    ///Bits 20:21 - Port x configuration pin 10
259    #[inline(always)]
260    pub fn ospeedr10(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
261        OSPEEDR_W::new(self, 20)
262    }
263    ///Bits 22:23 - Port x configuration pin 11
264    #[inline(always)]
265    pub fn ospeedr11(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
266        OSPEEDR_W::new(self, 22)
267    }
268    ///Bits 24:25 - Port x configuration pin 12
269    #[inline(always)]
270    pub fn ospeedr12(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
271        OSPEEDR_W::new(self, 24)
272    }
273    ///Bits 26:27 - Port x configuration pin 13
274    #[inline(always)]
275    pub fn ospeedr13(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
276        OSPEEDR_W::new(self, 26)
277    }
278    ///Bits 28:29 - Port x configuration pin 14
279    #[inline(always)]
280    pub fn ospeedr14(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
281        OSPEEDR_W::new(self, 28)
282    }
283    ///Bits 30:31 - Port x configuration pin 15
284    #[inline(always)]
285    pub fn ospeedr15(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
286        OSPEEDR_W::new(self, 30)
287    }
288}
289/**GPIO port output speed register
290
291You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
292
293See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOC:OSPEEDR)*/
294pub struct OSPEEDRrs;
295impl crate::RegisterSpec for OSPEEDRrs {
296    type Ux = u32;
297}
298///`read()` method returns [`ospeedr::R`](R) reader structure
299impl crate::Readable for OSPEEDRrs {}
300///`write(|w| ..)` method takes [`ospeedr::W`](W) writer structure
301impl crate::Writable for OSPEEDRrs {
302    type Safety = crate::Unsafe;
303    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
304    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
305}
306///`reset()` method sets OSPEEDR to value 0
307impl crate::Resettable for OSPEEDRrs {
308    const RESET_VALUE: u32 = 0;
309}
stm32f3_staging/stm32f373/gpioc/ospeedr.rs

stm32f3_staging/stm32f373/gpioc/
ospeedr.rs
