stm32f3_staging/stm32f373/
gpioa.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    moder: MODER,
6    otyper: OTYPER,
7    ospeedr: OSPEEDR,
8    pupdr: PUPDR,
9    idr: IDR,
10    odr: ODR,
11    bsrr: BSRR,
12    lckr: LCKR,
13    afrl: AFRL,
14    afrh: AFRH,
15    brr: BRR,
16}
17impl RegisterBlock {
18    ///0x00 - GPIO port mode register
19    #[inline(always)]
20    pub const fn moder(&self) -> &MODER {
21        &self.moder
22    }
23    ///0x04 - GPIO port output type register
24    #[inline(always)]
25    pub const fn otyper(&self) -> &OTYPER {
26        &self.otyper
27    }
28    ///0x08 - GPIO port output speed register
29    #[inline(always)]
30    pub const fn ospeedr(&self) -> &OSPEEDR {
31        &self.ospeedr
32    }
33    ///0x0c - GPIO port pull-up/pull-down register
34    #[inline(always)]
35    pub const fn pupdr(&self) -> &PUPDR {
36        &self.pupdr
37    }
38    ///0x10 - GPIO port input data register
39    #[inline(always)]
40    pub const fn idr(&self) -> &IDR {
41        &self.idr
42    }
43    ///0x14 - GPIO port output data register
44    #[inline(always)]
45    pub const fn odr(&self) -> &ODR {
46        &self.odr
47    }
48    ///0x18 - GPIO port bit set/reset register
49    #[inline(always)]
50    pub const fn bsrr(&self) -> &BSRR {
51        &self.bsrr
52    }
53    ///0x1c - GPIO port configuration lock register
54    #[inline(always)]
55    pub const fn lckr(&self) -> &LCKR {
56        &self.lckr
57    }
58    ///0x20 - GPIO alternate function low register
59    #[inline(always)]
60    pub const fn afrl(&self) -> &AFRL {
61        &self.afrl
62    }
63    ///0x24 - GPIO alternate function high register
64    #[inline(always)]
65    pub const fn afrh(&self) -> &AFRH {
66        &self.afrh
67    }
68    ///0x28 - Port bit reset register
69    #[inline(always)]
70    pub const fn brr(&self) -> &BRR {
71        &self.brr
72    }
73}
74/**MODER (rw) register accessor: GPIO port mode register
75
76You can [`read`](crate::Reg::read) this register and get [`moder::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`moder::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
77
78See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:MODER)
79
80For information about available fields see [`mod@moder`]
81module*/
82pub type MODER = crate::Reg<moder::MODERrs>;
83///GPIO port mode register
84pub mod moder;
85/**OTYPER (rw) register accessor: GPIO port output type register
86
87You can [`read`](crate::Reg::read) this register and get [`otyper::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otyper::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
88
89See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:OTYPER)
90
91For information about available fields see [`mod@otyper`]
92module*/
93pub type OTYPER = crate::Reg<otyper::OTYPERrs>;
94///GPIO port output type register
95pub mod otyper;
96/**OSPEEDR (rw) register accessor: GPIO port output speed register
97
98You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:OSPEEDR)
101
102For information about available fields see [`mod@ospeedr`]
103module*/
104pub type OSPEEDR = crate::Reg<ospeedr::OSPEEDRrs>;
105///GPIO port output speed register
106pub mod ospeedr;
107/**PUPDR (rw) register accessor: GPIO port pull-up/pull-down register
108
109You can [`read`](crate::Reg::read) this register and get [`pupdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pupdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
110
111See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:PUPDR)
112
113For information about available fields see [`mod@pupdr`]
114module*/
115pub type PUPDR = crate::Reg<pupdr::PUPDRrs>;
116///GPIO port pull-up/pull-down register
117pub mod pupdr;
118/**IDR (r) register accessor: GPIO port input data register
119
120You can [`read`](crate::Reg::read) this register and get [`idr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:IDR)
123
124For information about available fields see [`mod@idr`]
125module*/
126pub type IDR = crate::Reg<idr::IDRrs>;
127///GPIO port input data register
128pub mod idr;
129/**ODR (rw) register accessor: GPIO port output data register
130
131You can [`read`](crate::Reg::read) this register and get [`odr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`odr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:ODR)
134
135For information about available fields see [`mod@odr`]
136module*/
137pub type ODR = crate::Reg<odr::ODRrs>;
138///GPIO port output data register
139pub mod odr;
140/**BSRR (w) register accessor: GPIO port bit set/reset register
141
142You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bsrr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:BSRR)
145
146For information about available fields see [`mod@bsrr`]
147module*/
148pub type BSRR = crate::Reg<bsrr::BSRRrs>;
149///GPIO port bit set/reset register
150pub mod bsrr;
151/**LCKR (rw) register accessor: GPIO port configuration lock register
152
153You can [`read`](crate::Reg::read) this register and get [`lckr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lckr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
154
155See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:LCKR)
156
157For information about available fields see [`mod@lckr`]
158module*/
159pub type LCKR = crate::Reg<lckr::LCKRrs>;
160///GPIO port configuration lock register
161pub mod lckr;
162/**AFRL (rw) register accessor: GPIO alternate function low register
163
164You can [`read`](crate::Reg::read) this register and get [`afrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`afrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
165
166See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:AFRL)
167
168For information about available fields see [`mod@afrl`]
169module*/
170pub type AFRL = crate::Reg<afrl::AFRLrs>;
171///GPIO alternate function low register
172pub mod afrl;
173/**AFRH (rw) register accessor: GPIO alternate function high register
174
175You can [`read`](crate::Reg::read) this register and get [`afrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`afrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
176
177See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:AFRH)
178
179For information about available fields see [`mod@afrh`]
180module*/
181pub type AFRH = crate::Reg<afrh::AFRHrs>;
182///GPIO alternate function high register
183pub mod afrh;
184/**BRR (w) register accessor: Port bit reset register
185
186You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
187
188See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#GPIOA:BRR)
189
190For information about available fields see [`mod@brr`]
191module*/
192pub type BRR = crate::Reg<brr::BRRrs>;
193///Port bit reset register
194pub mod brr;
stm32f3_staging/stm32f373/gpioa.rs

stm32f3_staging/stm32f373/
gpioa.rs
