stm32f3_staging/stm32f373/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5/**LATENCY
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum LATENCY {
12    ///0: 0 wait states, if 0 < HCLK <= 24 MHz
13    Ws0 = 0,
14    ///1: 1 wait state, if 24 < HCLK <= 48 MHz
15    Ws1 = 1,
16    ///2: 2 wait states, if 48 < HCLK <= 72 MHz
17    Ws2 = 2,
18}
19impl From<LATENCY> for u8 {
20    #[inline(always)]
21    fn from(variant: LATENCY) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for LATENCY {
26    type Ux = u8;
27}
28impl crate::IsEnum for LATENCY {}
29///Field `LATENCY` reader - LATENCY
30pub type LATENCY_R = crate::FieldReader<LATENCY>;
31impl LATENCY_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<LATENCY> {
35        match self.bits {
36            0 => Some(LATENCY::Ws0),
37            1 => Some(LATENCY::Ws1),
38            2 => Some(LATENCY::Ws2),
39            _ => None,
40        }
41    }
42    ///0 wait states, if 0 < HCLK <= 24 MHz
43    #[inline(always)]
44    pub fn is_ws0(&self) -> bool {
45        *self == LATENCY::Ws0
46    }
47    ///1 wait state, if 24 < HCLK <= 48 MHz
48    #[inline(always)]
49    pub fn is_ws1(&self) -> bool {
50        *self == LATENCY::Ws1
51    }
52    ///2 wait states, if 48 < HCLK <= 72 MHz
53    #[inline(always)]
54    pub fn is_ws2(&self) -> bool {
55        *self == LATENCY::Ws2
56    }
57}
58///Field `LATENCY` writer - LATENCY
59pub type LATENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 3, LATENCY>;
60impl<'a, REG> LATENCY_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///0 wait states, if 0 < HCLK <= 24 MHz
66    #[inline(always)]
67    pub fn ws0(self) -> &'a mut crate::W<REG> {
68        self.variant(LATENCY::Ws0)
69    }
70    ///1 wait state, if 24 < HCLK <= 48 MHz
71    #[inline(always)]
72    pub fn ws1(self) -> &'a mut crate::W<REG> {
73        self.variant(LATENCY::Ws1)
74    }
75    ///2 wait states, if 48 < HCLK <= 72 MHz
76    #[inline(always)]
77    pub fn ws2(self) -> &'a mut crate::W<REG> {
78        self.variant(LATENCY::Ws2)
79    }
80}
81/**PRFTBE
82
83Value on reset: 1*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum PRFTBE {
87    ///0: Prefetch is disabled
88    Disabled = 0,
89    ///1: Prefetch is enabled
90    Enabled = 1,
91}
92impl From<PRFTBE> for bool {
93    #[inline(always)]
94    fn from(variant: PRFTBE) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `PRFTBE` reader - PRFTBE
99pub type PRFTBE_R = crate::BitReader<PRFTBE>;
100impl PRFTBE_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> PRFTBE {
104        match self.bits {
105            false => PRFTBE::Disabled,
106            true => PRFTBE::Enabled,
107        }
108    }
109    ///Prefetch is disabled
110    #[inline(always)]
111    pub fn is_disabled(&self) -> bool {
112        *self == PRFTBE::Disabled
113    }
114    ///Prefetch is enabled
115    #[inline(always)]
116    pub fn is_enabled(&self) -> bool {
117        *self == PRFTBE::Enabled
118    }
119}
120///Field `PRFTBE` writer - PRFTBE
121pub type PRFTBE_W<'a, REG> = crate::BitWriter<'a, REG, PRFTBE>;
122impl<'a, REG> PRFTBE_W<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125{
126    ///Prefetch is disabled
127    #[inline(always)]
128    pub fn disabled(self) -> &'a mut crate::W<REG> {
129        self.variant(PRFTBE::Disabled)
130    }
131    ///Prefetch is enabled
132    #[inline(always)]
133    pub fn enabled(self) -> &'a mut crate::W<REG> {
134        self.variant(PRFTBE::Enabled)
135    }
136}
137/**PRFTBS
138
139Value on reset: 1*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum PRFTBS {
143    ///0: Prefetch buffer is disabled
144    Disabled = 0,
145    ///1: Prefetch buffer is enabled
146    Enabled = 1,
147}
148impl From<PRFTBS> for bool {
149    #[inline(always)]
150    fn from(variant: PRFTBS) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `PRFTBS` reader - PRFTBS
155pub type PRFTBS_R = crate::BitReader<PRFTBS>;
156impl PRFTBS_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> PRFTBS {
160        match self.bits {
161            false => PRFTBS::Disabled,
162            true => PRFTBS::Enabled,
163        }
164    }
165    ///Prefetch buffer is disabled
166    #[inline(always)]
167    pub fn is_disabled(&self) -> bool {
168        *self == PRFTBS::Disabled
169    }
170    ///Prefetch buffer is enabled
171    #[inline(always)]
172    pub fn is_enabled(&self) -> bool {
173        *self == PRFTBS::Enabled
174    }
175}
176impl R {
177    ///Bits 0:2 - LATENCY
178    #[inline(always)]
179    pub fn latency(&self) -> LATENCY_R {
180        LATENCY_R::new((self.bits & 7) as u8)
181    }
182    ///Bit 4 - PRFTBE
183    #[inline(always)]
184    pub fn prftbe(&self) -> PRFTBE_R {
185        PRFTBE_R::new(((self.bits >> 4) & 1) != 0)
186    }
187    ///Bit 5 - PRFTBS
188    #[inline(always)]
189    pub fn prftbs(&self) -> PRFTBS_R {
190        PRFTBS_R::new(((self.bits >> 5) & 1) != 0)
191    }
192}
193impl core::fmt::Debug for R {
194    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
195        f.debug_struct("ACR")
196            .field("latency", &self.latency())
197            .field("prftbe", &self.prftbe())
198            .field("prftbs", &self.prftbs())
199            .finish()
200    }
201}
202impl W {
203    ///Bits 0:2 - LATENCY
204    #[inline(always)]
205    pub fn latency(&mut self) -> LATENCY_W<ACRrs> {
206        LATENCY_W::new(self, 0)
207    }
208    ///Bit 4 - PRFTBE
209    #[inline(always)]
210    pub fn prftbe(&mut self) -> PRFTBE_W<ACRrs> {
211        PRFTBE_W::new(self, 4)
212    }
213}
214/**Flash access control register
215
216You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
217
218See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#FLASH:ACR)*/
219pub struct ACRrs;
220impl crate::RegisterSpec for ACRrs {
221    type Ux = u32;
222}
223///`read()` method returns [`acr::R`](R) reader structure
224impl crate::Readable for ACRrs {}
225///`write(|w| ..)` method takes [`acr::W`](W) writer structure
226impl crate::Writable for ACRrs {
227    type Safety = crate::Unsafe;
228    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
229    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
230}
231///`reset()` method sets ACR to value 0x30
232impl crate::Resettable for ACRrs {
233    const RESET_VALUE: u32 = 0x30;
234}
stm32f3_staging/stm32f373/flash/acr.rs

stm32f3_staging/stm32f373/flash/
acr.rs
