stm32f3_staging/stm32f373/
dac1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    swtrigr: SWTRIGR,
7    dhr12r1: DHR12R1,
8    dhr12l1: DHR12L1,
9    dhr8r1: DHR8R1,
10    dhr12r2: DHR12R2,
11    dhr12l2: DHR12L2,
12    dhr8r2: DHR8R2,
13    dhr12rd: DHR12RD,
14    dhr12ld: DHR12LD,
15    dhr8rd: DHR8RD,
16    dor1: DOR1,
17    dor2: DOR2,
18    sr: SR,
19}
20impl RegisterBlock {
21    ///0x00 - control register
22    #[inline(always)]
23    pub const fn cr(&self) -> &CR {
24        &self.cr
25    }
26    ///0x04 - software trigger register
27    #[inline(always)]
28    pub const fn swtrigr(&self) -> &SWTRIGR {
29        &self.swtrigr
30    }
31    ///0x08 - channel1 12-bit right-aligned data holding register
32    #[inline(always)]
33    pub const fn dhr12r1(&self) -> &DHR12R1 {
34        &self.dhr12r1
35    }
36    ///0x0c - channel1 12-bit left aligned data holding register
37    #[inline(always)]
38    pub const fn dhr12l1(&self) -> &DHR12L1 {
39        &self.dhr12l1
40    }
41    ///0x10 - channel1 8-bit right aligned data holding register
42    #[inline(always)]
43    pub const fn dhr8r1(&self) -> &DHR8R1 {
44        &self.dhr8r1
45    }
46    ///0x14 - channel2 12-bit right aligned data holding register
47    #[inline(always)]
48    pub const fn dhr12r2(&self) -> &DHR12R2 {
49        &self.dhr12r2
50    }
51    ///0x18 - channel2 12-bit left aligned data holding register
52    #[inline(always)]
53    pub const fn dhr12l2(&self) -> &DHR12L2 {
54        &self.dhr12l2
55    }
56    ///0x1c - channel2 8-bit right-aligned data holding register
57    #[inline(always)]
58    pub const fn dhr8r2(&self) -> &DHR8R2 {
59        &self.dhr8r2
60    }
61    ///0x20 - Dual DAC 12-bit right-aligned data holding register
62    #[inline(always)]
63    pub const fn dhr12rd(&self) -> &DHR12RD {
64        &self.dhr12rd
65    }
66    ///0x24 - DUAL DAC 12-bit left aligned data holding register
67    #[inline(always)]
68    pub const fn dhr12ld(&self) -> &DHR12LD {
69        &self.dhr12ld
70    }
71    ///0x28 - DUAL DAC 8-bit right aligned data holding register
72    #[inline(always)]
73    pub const fn dhr8rd(&self) -> &DHR8RD {
74        &self.dhr8rd
75    }
76    ///0x2c - channel1 data output register
77    #[inline(always)]
78    pub const fn dor1(&self) -> &DOR1 {
79        &self.dor1
80    }
81    ///0x30 - channel2 data output register
82    #[inline(always)]
83    pub const fn dor2(&self) -> &DOR2 {
84        &self.dor2
85    }
86    ///0x34 - status register
87    #[inline(always)]
88    pub const fn sr(&self) -> &SR {
89        &self.sr
90    }
91}
92/**CR (rw) register accessor: control register
93
94You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
95
96See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:CR)
97
98For information about available fields see [`mod@cr`]
99module*/
100pub type CR = crate::Reg<cr::CRrs>;
101///control register
102pub mod cr;
103/**SWTRIGR (w) register accessor: software trigger register
104
105You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrigr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
106
107See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:SWTRIGR)
108
109For information about available fields see [`mod@swtrigr`]
110module*/
111pub type SWTRIGR = crate::Reg<swtrigr::SWTRIGRrs>;
112///software trigger register
113pub mod swtrigr;
114/**DHR12R1 (rw) register accessor: channel1 12-bit right-aligned data holding register
115
116You can [`read`](crate::Reg::read) this register and get [`dhr12r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
117
118See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR12R1)
119
120For information about available fields see [`mod@dhr12r1`]
121module*/
122pub type DHR12R1 = crate::Reg<dhr12r1::DHR12R1rs>;
123///channel1 12-bit right-aligned data holding register
124pub mod dhr12r1;
125/**DHR12L1 (rw) register accessor: channel1 12-bit left aligned data holding register
126
127You can [`read`](crate::Reg::read) this register and get [`dhr12l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
128
129See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR12L1)
130
131For information about available fields see [`mod@dhr12l1`]
132module*/
133pub type DHR12L1 = crate::Reg<dhr12l1::DHR12L1rs>;
134///channel1 12-bit left aligned data holding register
135pub mod dhr12l1;
136/**DHR8R1 (rw) register accessor: channel1 8-bit right aligned data holding register
137
138You can [`read`](crate::Reg::read) this register and get [`dhr8r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
139
140See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR8R1)
141
142For information about available fields see [`mod@dhr8r1`]
143module*/
144pub type DHR8R1 = crate::Reg<dhr8r1::DHR8R1rs>;
145///channel1 8-bit right aligned data holding register
146pub mod dhr8r1;
147/**DHR12R2 (rw) register accessor: channel2 12-bit right aligned data holding register
148
149You can [`read`](crate::Reg::read) this register and get [`dhr12r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
150
151See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR12R2)
152
153For information about available fields see [`mod@dhr12r2`]
154module*/
155pub type DHR12R2 = crate::Reg<dhr12r2::DHR12R2rs>;
156///channel2 12-bit right aligned data holding register
157pub mod dhr12r2;
158/**DHR12L2 (rw) register accessor: channel2 12-bit left aligned data holding register
159
160You can [`read`](crate::Reg::read) this register and get [`dhr12l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR12L2)
163
164For information about available fields see [`mod@dhr12l2`]
165module*/
166pub type DHR12L2 = crate::Reg<dhr12l2::DHR12L2rs>;
167///channel2 12-bit left aligned data holding register
168pub mod dhr12l2;
169/**DHR8R2 (rw) register accessor: channel2 8-bit right-aligned data holding register
170
171You can [`read`](crate::Reg::read) this register and get [`dhr8r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
172
173See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR8R2)
174
175For information about available fields see [`mod@dhr8r2`]
176module*/
177pub type DHR8R2 = crate::Reg<dhr8r2::DHR8R2rs>;
178///channel2 8-bit right-aligned data holding register
179pub mod dhr8r2;
180/**DHR12RD (rw) register accessor: Dual DAC 12-bit right-aligned data holding register
181
182You can [`read`](crate::Reg::read) this register and get [`dhr12rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR12RD)
185
186For information about available fields see [`mod@dhr12rd`]
187module*/
188pub type DHR12RD = crate::Reg<dhr12rd::DHR12RDrs>;
189///Dual DAC 12-bit right-aligned data holding register
190pub mod dhr12rd;
191/**DHR12LD (rw) register accessor: DUAL DAC 12-bit left aligned data holding register
192
193You can [`read`](crate::Reg::read) this register and get [`dhr12ld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12ld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
194
195See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR12LD)
196
197For information about available fields see [`mod@dhr12ld`]
198module*/
199pub type DHR12LD = crate::Reg<dhr12ld::DHR12LDrs>;
200///DUAL DAC 12-bit left aligned data holding register
201pub mod dhr12ld;
202/**DHR8RD (rw) register accessor: DUAL DAC 8-bit right aligned data holding register
203
204You can [`read`](crate::Reg::read) this register and get [`dhr8rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
205
206See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DHR8RD)
207
208For information about available fields see [`mod@dhr8rd`]
209module*/
210pub type DHR8RD = crate::Reg<dhr8rd::DHR8RDrs>;
211///DUAL DAC 8-bit right aligned data holding register
212pub mod dhr8rd;
213/**DOR1 (r) register accessor: channel1 data output register
214
215You can [`read`](crate::Reg::read) this register and get [`dor1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
216
217See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DOR1)
218
219For information about available fields see [`mod@dor1`]
220module*/
221pub type DOR1 = crate::Reg<dor1::DOR1rs>;
222///channel1 data output register
223pub mod dor1;
224/**DOR2 (r) register accessor: channel2 data output register
225
226You can [`read`](crate::Reg::read) this register and get [`dor2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
227
228See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:DOR2)
229
230For information about available fields see [`mod@dor2`]
231module*/
232pub type DOR2 = crate::Reg<dor2::DOR2rs>;
233///channel2 data output register
234pub mod dor2;
235/**SR (rw) register accessor: status register
236
237You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
238
239See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#DAC1:SR)
240
241For information about available fields see [`mod@sr`]
242module*/
243pub type SR = crate::Reg<sr::SRrs>;
244///status register
245pub mod sr;
stm32f3_staging/stm32f373/dac1.rs

stm32f3_staging/stm32f373/
dac1.rs
