stm32f3_staging/stm32f373/comp/
csr.rs

1///Register `CSR` reader
2pub type R = crate::R<CSRrs>;
3///Register `CSR` writer
4pub type W = crate::W<CSRrs>;
5///Field `COMP1EN` reader - Comparator 1 enable
6pub type COMP1EN_R = crate::BitReader;
7///Field `COMP1EN` writer - Comparator 1 enable
8pub type COMP1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `COMP1_INP_DAC` reader - Comparator 1 non inverting input connection to DAC output
10pub type COMP1_INP_DAC_R = crate::BitReader;
11///Field `COMP1_INP_DAC` writer - Comparator 1 non inverting input connection to DAC output
12pub type COMP1_INP_DAC_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `COMP1MODE` reader - Comparator 1 mode
14pub type COMP1MODE_R = crate::FieldReader;
15///Field `COMP1MODE` writer - Comparator 1 mode
16pub type COMP1MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17///Field `COMP1INSEL` reader - Comparator 1 inverting input selection
18pub type COMP1INSEL_R = crate::FieldReader;
19///Field `COMP1INSEL` writer - Comparator 1 inverting input selection
20pub type COMP1INSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21///Field `COMP1OUTSEL` reader - Comparator 1 output selection
22pub type COMP1OUTSEL_R = crate::FieldReader;
23///Field `COMP1OUTSEL` writer - Comparator 1 output selection
24pub type COMP1OUTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25///Field `COMP1POL` reader - Comparator 1 output polarity
26pub type COMP1POL_R = crate::BitReader;
27///Field `COMP1POL` writer - Comparator 1 output polarity
28pub type COMP1POL_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `COMP1HYST` reader - Comparator 1 hysteresis
30pub type COMP1HYST_R = crate::FieldReader;
31///Field `COMP1HYST` writer - Comparator 1 hysteresis
32pub type COMP1HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33///Field `COMP1OUT` reader - Comparator 1 output
34pub type COMP1OUT_R = crate::BitReader;
35///Field `COMP1LOCK` reader - Comparator 1 lock
36pub type COMP1LOCK_R = crate::BitReader;
37///Field `COMP1LOCK` writer - Comparator 1 lock
38pub type COMP1LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
39///Field `COMP2EN` reader - Comparator 2 enable
40pub type COMP2EN_R = crate::BitReader;
41///Field `COMP2EN` writer - Comparator 2 enable
42pub type COMP2EN_W<'a, REG> = crate::BitWriter<'a, REG>;
43///Field `COMP2MODE` reader - Comparator 2 mode
44pub type COMP2MODE_R = crate::FieldReader;
45///Field `COMP2MODE` writer - Comparator 2 mode
46pub type COMP2MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
47///Field `COMP2INSEL` reader - Comparator 2 inverting input selection
48pub type COMP2INSEL_R = crate::FieldReader;
49///Field `COMP2INSEL` writer - Comparator 2 inverting input selection
50pub type COMP2INSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
51///Field `WNDWEN` reader - Window mode enable
52pub type WNDWEN_R = crate::BitReader;
53///Field `WNDWEN` writer - Window mode enable
54pub type WNDWEN_W<'a, REG> = crate::BitWriter<'a, REG>;
55///Field `COMP2OUTSEL` reader - Comparator 2 output selection
56pub type COMP2OUTSEL_R = crate::FieldReader;
57///Field `COMP2OUTSEL` writer - Comparator 2 output selection
58pub type COMP2OUTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
59///Field `COMP2POL` reader - Comparator 2 output polarity
60pub type COMP2POL_R = crate::BitReader;
61///Field `COMP2POL` writer - Comparator 2 output polarity
62pub type COMP2POL_W<'a, REG> = crate::BitWriter<'a, REG>;
63///Field `COMP2HYST` reader - Comparator 2 hysteresis
64pub type COMP2HYST_R = crate::FieldReader;
65///Field `COMP2HYST` writer - Comparator 2 hysteresis
66pub type COMP2HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
67///Field `COMP2OUT` reader - Comparator 2 output
68pub type COMP2OUT_R = crate::BitReader;
69///Field `COMP2LOCK` reader - Comparator 2 lock
70pub type COMP2LOCK_R = crate::BitReader;
71///Field `COMP2LOCK` writer - Comparator 2 lock
72pub type COMP2LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74    ///Bit 0 - Comparator 1 enable
75    #[inline(always)]
76    pub fn comp1en(&self) -> COMP1EN_R {
77        COMP1EN_R::new((self.bits & 1) != 0)
78    }
79    ///Bit 1 - Comparator 1 non inverting input connection to DAC output
80    #[inline(always)]
81    pub fn comp1_inp_dac(&self) -> COMP1_INP_DAC_R {
82        COMP1_INP_DAC_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    ///Bits 2:3 - Comparator 1 mode
85    #[inline(always)]
86    pub fn comp1mode(&self) -> COMP1MODE_R {
87        COMP1MODE_R::new(((self.bits >> 2) & 3) as u8)
88    }
89    ///Bits 4:6 - Comparator 1 inverting input selection
90    #[inline(always)]
91    pub fn comp1insel(&self) -> COMP1INSEL_R {
92        COMP1INSEL_R::new(((self.bits >> 4) & 7) as u8)
93    }
94    ///Bits 8:10 - Comparator 1 output selection
95    #[inline(always)]
96    pub fn comp1outsel(&self) -> COMP1OUTSEL_R {
97        COMP1OUTSEL_R::new(((self.bits >> 8) & 7) as u8)
98    }
99    ///Bit 11 - Comparator 1 output polarity
100    #[inline(always)]
101    pub fn comp1pol(&self) -> COMP1POL_R {
102        COMP1POL_R::new(((self.bits >> 11) & 1) != 0)
103    }
104    ///Bits 12:13 - Comparator 1 hysteresis
105    #[inline(always)]
106    pub fn comp1hyst(&self) -> COMP1HYST_R {
107        COMP1HYST_R::new(((self.bits >> 12) & 3) as u8)
108    }
109    ///Bit 14 - Comparator 1 output
110    #[inline(always)]
111    pub fn comp1out(&self) -> COMP1OUT_R {
112        COMP1OUT_R::new(((self.bits >> 14) & 1) != 0)
113    }
114    ///Bit 15 - Comparator 1 lock
115    #[inline(always)]
116    pub fn comp1lock(&self) -> COMP1LOCK_R {
117        COMP1LOCK_R::new(((self.bits >> 15) & 1) != 0)
118    }
119    ///Bit 16 - Comparator 2 enable
120    #[inline(always)]
121    pub fn comp2en(&self) -> COMP2EN_R {
122        COMP2EN_R::new(((self.bits >> 16) & 1) != 0)
123    }
124    ///Bits 18:19 - Comparator 2 mode
125    #[inline(always)]
126    pub fn comp2mode(&self) -> COMP2MODE_R {
127        COMP2MODE_R::new(((self.bits >> 18) & 3) as u8)
128    }
129    ///Bits 20:22 - Comparator 2 inverting input selection
130    #[inline(always)]
131    pub fn comp2insel(&self) -> COMP2INSEL_R {
132        COMP2INSEL_R::new(((self.bits >> 20) & 7) as u8)
133    }
134    ///Bit 23 - Window mode enable
135    #[inline(always)]
136    pub fn wndwen(&self) -> WNDWEN_R {
137        WNDWEN_R::new(((self.bits >> 23) & 1) != 0)
138    }
139    ///Bits 24:26 - Comparator 2 output selection
140    #[inline(always)]
141    pub fn comp2outsel(&self) -> COMP2OUTSEL_R {
142        COMP2OUTSEL_R::new(((self.bits >> 24) & 7) as u8)
143    }
144    ///Bit 27 - Comparator 2 output polarity
145    #[inline(always)]
146    pub fn comp2pol(&self) -> COMP2POL_R {
147        COMP2POL_R::new(((self.bits >> 27) & 1) != 0)
148    }
149    ///Bits 28:29 - Comparator 2 hysteresis
150    #[inline(always)]
151    pub fn comp2hyst(&self) -> COMP2HYST_R {
152        COMP2HYST_R::new(((self.bits >> 28) & 3) as u8)
153    }
154    ///Bit 30 - Comparator 2 output
155    #[inline(always)]
156    pub fn comp2out(&self) -> COMP2OUT_R {
157        COMP2OUT_R::new(((self.bits >> 30) & 1) != 0)
158    }
159    ///Bit 31 - Comparator 2 lock
160    #[inline(always)]
161    pub fn comp2lock(&self) -> COMP2LOCK_R {
162        COMP2LOCK_R::new(((self.bits >> 31) & 1) != 0)
163    }
164}
165impl core::fmt::Debug for R {
166    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
167        f.debug_struct("CSR")
168            .field("comp1en", &self.comp1en())
169            .field("comp1mode", &self.comp1mode())
170            .field("comp1insel", &self.comp1insel())
171            .field("comp1outsel", &self.comp1outsel())
172            .field("comp1pol", &self.comp1pol())
173            .field("comp1hyst", &self.comp1hyst())
174            .field("comp1out", &self.comp1out())
175            .field("comp1lock", &self.comp1lock())
176            .field("comp2en", &self.comp2en())
177            .field("comp2mode", &self.comp2mode())
178            .field("comp2insel", &self.comp2insel())
179            .field("wndwen", &self.wndwen())
180            .field("comp2outsel", &self.comp2outsel())
181            .field("comp2pol", &self.comp2pol())
182            .field("comp2hyst", &self.comp2hyst())
183            .field("comp2out", &self.comp2out())
184            .field("comp2lock", &self.comp2lock())
185            .field("comp1_inp_dac", &self.comp1_inp_dac())
186            .finish()
187    }
188}
189impl W {
190    ///Bit 0 - Comparator 1 enable
191    #[inline(always)]
192    pub fn comp1en(&mut self) -> COMP1EN_W<CSRrs> {
193        COMP1EN_W::new(self, 0)
194    }
195    ///Bit 1 - Comparator 1 non inverting input connection to DAC output
196    #[inline(always)]
197    pub fn comp1_inp_dac(&mut self) -> COMP1_INP_DAC_W<CSRrs> {
198        COMP1_INP_DAC_W::new(self, 1)
199    }
200    ///Bits 2:3 - Comparator 1 mode
201    #[inline(always)]
202    pub fn comp1mode(&mut self) -> COMP1MODE_W<CSRrs> {
203        COMP1MODE_W::new(self, 2)
204    }
205    ///Bits 4:6 - Comparator 1 inverting input selection
206    #[inline(always)]
207    pub fn comp1insel(&mut self) -> COMP1INSEL_W<CSRrs> {
208        COMP1INSEL_W::new(self, 4)
209    }
210    ///Bits 8:10 - Comparator 1 output selection
211    #[inline(always)]
212    pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<CSRrs> {
213        COMP1OUTSEL_W::new(self, 8)
214    }
215    ///Bit 11 - Comparator 1 output polarity
216    #[inline(always)]
217    pub fn comp1pol(&mut self) -> COMP1POL_W<CSRrs> {
218        COMP1POL_W::new(self, 11)
219    }
220    ///Bits 12:13 - Comparator 1 hysteresis
221    #[inline(always)]
222    pub fn comp1hyst(&mut self) -> COMP1HYST_W<CSRrs> {
223        COMP1HYST_W::new(self, 12)
224    }
225    ///Bit 15 - Comparator 1 lock
226    #[inline(always)]
227    pub fn comp1lock(&mut self) -> COMP1LOCK_W<CSRrs> {
228        COMP1LOCK_W::new(self, 15)
229    }
230    ///Bit 16 - Comparator 2 enable
231    #[inline(always)]
232    pub fn comp2en(&mut self) -> COMP2EN_W<CSRrs> {
233        COMP2EN_W::new(self, 16)
234    }
235    ///Bits 18:19 - Comparator 2 mode
236    #[inline(always)]
237    pub fn comp2mode(&mut self) -> COMP2MODE_W<CSRrs> {
238        COMP2MODE_W::new(self, 18)
239    }
240    ///Bits 20:22 - Comparator 2 inverting input selection
241    #[inline(always)]
242    pub fn comp2insel(&mut self) -> COMP2INSEL_W<CSRrs> {
243        COMP2INSEL_W::new(self, 20)
244    }
245    ///Bit 23 - Window mode enable
246    #[inline(always)]
247    pub fn wndwen(&mut self) -> WNDWEN_W<CSRrs> {
248        WNDWEN_W::new(self, 23)
249    }
250    ///Bits 24:26 - Comparator 2 output selection
251    #[inline(always)]
252    pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<CSRrs> {
253        COMP2OUTSEL_W::new(self, 24)
254    }
255    ///Bit 27 - Comparator 2 output polarity
256    #[inline(always)]
257    pub fn comp2pol(&mut self) -> COMP2POL_W<CSRrs> {
258        COMP2POL_W::new(self, 27)
259    }
260    ///Bits 28:29 - Comparator 2 hysteresis
261    #[inline(always)]
262    pub fn comp2hyst(&mut self) -> COMP2HYST_W<CSRrs> {
263        COMP2HYST_W::new(self, 28)
264    }
265    ///Bit 31 - Comparator 2 lock
266    #[inline(always)]
267    pub fn comp2lock(&mut self) -> COMP2LOCK_W<CSRrs> {
268        COMP2LOCK_W::new(self, 31)
269    }
270}
271/**control and status register
272
273You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
274
275See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#COMP:CSR)*/
276pub struct CSRrs;
277impl crate::RegisterSpec for CSRrs {
278    type Ux = u32;
279}
280///`read()` method returns [`csr::R`](R) reader structure
281impl crate::Readable for CSRrs {}
282///`write(|w| ..)` method takes [`csr::W`](W) writer structure
283impl crate::Writable for CSRrs {
284    type Safety = crate::Unsafe;
285    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
286    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
287}
288///`reset()` method sets CSR to value 0
289impl crate::Resettable for CSRrs {
290    const RESET_VALUE: u32 = 0;
291}
stm32f3_staging/stm32f373/comp/csr.rs

stm32f3_staging/stm32f373/comp/
csr.rs
