stm32f3_staging/stm32f373/cec/
isr.rs

1///Register `ISR` reader
2pub type R = crate::R<ISRrs>;
3///Register `ISR` writer
4pub type W = crate::W<ISRrs>;
5///Field `RXBR` reader - Rx-Byte Received
6pub type RXBR_R = crate::BitReader;
7///Field `RXBR` writer - Rx-Byte Received
8pub type RXBR_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `RXEND` reader - End Of Reception
10pub type RXEND_R = crate::BitReader;
11///Field `RXEND` writer - End Of Reception
12pub type RXEND_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `RXOVR` reader - Rx-Overrun
14pub type RXOVR_R = crate::BitReader;
15///Field `RXOVR` writer - Rx-Overrun
16pub type RXOVR_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `BRE` reader - Rx-Bit rising error
18pub type BRE_R = crate::BitReader;
19///Field `BRE` writer - Rx-Bit rising error
20pub type BRE_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `SBPE` reader - Rx-Short Bit period error
22pub type SBPE_R = crate::BitReader;
23///Field `SBPE` writer - Rx-Short Bit period error
24pub type SBPE_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `LBPE` reader - Rx-Long Bit Period Error
26pub type LBPE_R = crate::BitReader;
27///Field `LBPE` writer - Rx-Long Bit Period Error
28pub type LBPE_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `RXACKE` reader - Rx-Missing Acknowledge
30pub type RXACKE_R = crate::BitReader;
31///Field `RXACKE` writer - Rx-Missing Acknowledge
32pub type RXACKE_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `ARBLST` reader - Arbitration Lost
34pub type ARBLST_R = crate::BitReader;
35///Field `ARBLST` writer - Arbitration Lost
36pub type ARBLST_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `TXBR` reader - Tx-Byte Request
38pub type TXBR_R = crate::BitReader;
39///Field `TXBR` writer - Tx-Byte Request
40pub type TXBR_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `TXEND` reader - End of Transmission
42pub type TXEND_R = crate::BitReader;
43///Field `TXEND` writer - End of Transmission
44pub type TXEND_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `TXUDR` reader - Tx-Buffer Underrun
46pub type TXUDR_R = crate::BitReader;
47///Field `TXUDR` writer - Tx-Buffer Underrun
48pub type TXUDR_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `TXERR` reader - Tx-Error
50pub type TXERR_R = crate::BitReader;
51///Field `TXERR` writer - Tx-Error
52pub type TXERR_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `TXACKE` reader - Tx-Missing acknowledge error
54pub type TXACKE_R = crate::BitReader;
55///Field `TXACKE` writer - Tx-Missing acknowledge error
56pub type TXACKE_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58    ///Bit 0 - Rx-Byte Received
59    #[inline(always)]
60    pub fn rxbr(&self) -> RXBR_R {
61        RXBR_R::new((self.bits & 1) != 0)
62    }
63    ///Bit 1 - End Of Reception
64    #[inline(always)]
65    pub fn rxend(&self) -> RXEND_R {
66        RXEND_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    ///Bit 2 - Rx-Overrun
69    #[inline(always)]
70    pub fn rxovr(&self) -> RXOVR_R {
71        RXOVR_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    ///Bit 3 - Rx-Bit rising error
74    #[inline(always)]
75    pub fn bre(&self) -> BRE_R {
76        BRE_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    ///Bit 4 - Rx-Short Bit period error
79    #[inline(always)]
80    pub fn sbpe(&self) -> SBPE_R {
81        SBPE_R::new(((self.bits >> 4) & 1) != 0)
82    }
83    ///Bit 5 - Rx-Long Bit Period Error
84    #[inline(always)]
85    pub fn lbpe(&self) -> LBPE_R {
86        LBPE_R::new(((self.bits >> 5) & 1) != 0)
87    }
88    ///Bit 6 - Rx-Missing Acknowledge
89    #[inline(always)]
90    pub fn rxacke(&self) -> RXACKE_R {
91        RXACKE_R::new(((self.bits >> 6) & 1) != 0)
92    }
93    ///Bit 7 - Arbitration Lost
94    #[inline(always)]
95    pub fn arblst(&self) -> ARBLST_R {
96        ARBLST_R::new(((self.bits >> 7) & 1) != 0)
97    }
98    ///Bit 8 - Tx-Byte Request
99    #[inline(always)]
100    pub fn txbr(&self) -> TXBR_R {
101        TXBR_R::new(((self.bits >> 8) & 1) != 0)
102    }
103    ///Bit 9 - End of Transmission
104    #[inline(always)]
105    pub fn txend(&self) -> TXEND_R {
106        TXEND_R::new(((self.bits >> 9) & 1) != 0)
107    }
108    ///Bit 10 - Tx-Buffer Underrun
109    #[inline(always)]
110    pub fn txudr(&self) -> TXUDR_R {
111        TXUDR_R::new(((self.bits >> 10) & 1) != 0)
112    }
113    ///Bit 11 - Tx-Error
114    #[inline(always)]
115    pub fn txerr(&self) -> TXERR_R {
116        TXERR_R::new(((self.bits >> 11) & 1) != 0)
117    }
118    ///Bit 12 - Tx-Missing acknowledge error
119    #[inline(always)]
120    pub fn txacke(&self) -> TXACKE_R {
121        TXACKE_R::new(((self.bits >> 12) & 1) != 0)
122    }
123}
124impl core::fmt::Debug for R {
125    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
126        f.debug_struct("ISR")
127            .field("txacke", &self.txacke())
128            .field("txerr", &self.txerr())
129            .field("txudr", &self.txudr())
130            .field("txend", &self.txend())
131            .field("txbr", &self.txbr())
132            .field("arblst", &self.arblst())
133            .field("rxacke", &self.rxacke())
134            .field("lbpe", &self.lbpe())
135            .field("sbpe", &self.sbpe())
136            .field("bre", &self.bre())
137            .field("rxovr", &self.rxovr())
138            .field("rxend", &self.rxend())
139            .field("rxbr", &self.rxbr())
140            .finish()
141    }
142}
143impl W {
144    ///Bit 0 - Rx-Byte Received
145    #[inline(always)]
146    pub fn rxbr(&mut self) -> RXBR_W<ISRrs> {
147        RXBR_W::new(self, 0)
148    }
149    ///Bit 1 - End Of Reception
150    #[inline(always)]
151    pub fn rxend(&mut self) -> RXEND_W<ISRrs> {
152        RXEND_W::new(self, 1)
153    }
154    ///Bit 2 - Rx-Overrun
155    #[inline(always)]
156    pub fn rxovr(&mut self) -> RXOVR_W<ISRrs> {
157        RXOVR_W::new(self, 2)
158    }
159    ///Bit 3 - Rx-Bit rising error
160    #[inline(always)]
161    pub fn bre(&mut self) -> BRE_W<ISRrs> {
162        BRE_W::new(self, 3)
163    }
164    ///Bit 4 - Rx-Short Bit period error
165    #[inline(always)]
166    pub fn sbpe(&mut self) -> SBPE_W<ISRrs> {
167        SBPE_W::new(self, 4)
168    }
169    ///Bit 5 - Rx-Long Bit Period Error
170    #[inline(always)]
171    pub fn lbpe(&mut self) -> LBPE_W<ISRrs> {
172        LBPE_W::new(self, 5)
173    }
174    ///Bit 6 - Rx-Missing Acknowledge
175    #[inline(always)]
176    pub fn rxacke(&mut self) -> RXACKE_W<ISRrs> {
177        RXACKE_W::new(self, 6)
178    }
179    ///Bit 7 - Arbitration Lost
180    #[inline(always)]
181    pub fn arblst(&mut self) -> ARBLST_W<ISRrs> {
182        ARBLST_W::new(self, 7)
183    }
184    ///Bit 8 - Tx-Byte Request
185    #[inline(always)]
186    pub fn txbr(&mut self) -> TXBR_W<ISRrs> {
187        TXBR_W::new(self, 8)
188    }
189    ///Bit 9 - End of Transmission
190    #[inline(always)]
191    pub fn txend(&mut self) -> TXEND_W<ISRrs> {
192        TXEND_W::new(self, 9)
193    }
194    ///Bit 10 - Tx-Buffer Underrun
195    #[inline(always)]
196    pub fn txudr(&mut self) -> TXUDR_W<ISRrs> {
197        TXUDR_W::new(self, 10)
198    }
199    ///Bit 11 - Tx-Error
200    #[inline(always)]
201    pub fn txerr(&mut self) -> TXERR_W<ISRrs> {
202        TXERR_W::new(self, 11)
203    }
204    ///Bit 12 - Tx-Missing acknowledge error
205    #[inline(always)]
206    pub fn txacke(&mut self) -> TXACKE_W<ISRrs> {
207        TXACKE_W::new(self, 12)
208    }
209}
210/**Interrupt and Status Register
211
212You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CEC:ISR)*/
215pub struct ISRrs;
216impl crate::RegisterSpec for ISRrs {
217    type Ux = u32;
218}
219///`read()` method returns [`isr::R`](R) reader structure
220impl crate::Readable for ISRrs {}
221///`write(|w| ..)` method takes [`isr::W`](W) writer structure
222impl crate::Writable for ISRrs {
223    type Safety = crate::Unsafe;
224    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
225    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
226}
227///`reset()` method sets ISR to value 0
228impl crate::Resettable for ISRrs {
229    const RESET_VALUE: u32 = 0;
230}
stm32f3_staging/stm32f373/cec/isr.rs

stm32f3_staging/stm32f373/cec/
isr.rs
