stm32f3_staging/stm32f373/cec/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `CECEN` reader - CEC Enable
6pub type CECEN_R = crate::BitReader;
7///Field `CECEN` writer - CEC Enable
8pub type CECEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `TXSOM` reader - Tx start of message
10pub type TXSOM_R = crate::BitReader;
11///Field `TXSOM` writer - Tx start of message
12pub type TXSOM_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `TXEOM` reader - Tx End Of Message
14pub type TXEOM_R = crate::BitReader;
15///Field `TXEOM` writer - Tx End Of Message
16pub type TXEOM_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bit 0 - CEC Enable
19    #[inline(always)]
20    pub fn cecen(&self) -> CECEN_R {
21        CECEN_R::new((self.bits & 1) != 0)
22    }
23    ///Bit 1 - Tx start of message
24    #[inline(always)]
25    pub fn txsom(&self) -> TXSOM_R {
26        TXSOM_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    ///Bit 2 - Tx End Of Message
29    #[inline(always)]
30    pub fn txeom(&self) -> TXEOM_R {
31        TXEOM_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("CR")
37            .field("txeom", &self.txeom())
38            .field("txsom", &self.txsom())
39            .field("cecen", &self.cecen())
40            .finish()
41    }
42}
43impl W {
44    ///Bit 0 - CEC Enable
45    #[inline(always)]
46    pub fn cecen(&mut self) -> CECEN_W<CRrs> {
47        CECEN_W::new(self, 0)
48    }
49    ///Bit 1 - Tx start of message
50    #[inline(always)]
51    pub fn txsom(&mut self) -> TXSOM_W<CRrs> {
52        TXSOM_W::new(self, 1)
53    }
54    ///Bit 2 - Tx End Of Message
55    #[inline(always)]
56    pub fn txeom(&mut self) -> TXEOM_W<CRrs> {
57        TXEOM_W::new(self, 2)
58    }
59}
60/**control register
61
62You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CEC:CR)*/
65pub struct CRrs;
66impl crate::RegisterSpec for CRrs {
67    type Ux = u32;
68}
69///`read()` method returns [`cr::R`](R) reader structure
70impl crate::Readable for CRrs {}
71///`write(|w| ..)` method takes [`cr::W`](W) writer structure
72impl crate::Writable for CRrs {
73    type Safety = crate::Unsafe;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76}
77///`reset()` method sets CR to value 0
78impl crate::Resettable for CRrs {
79    const RESET_VALUE: u32 = 0;
80}
stm32f3_staging/stm32f373/cec/cr.rs

stm32f3_staging/stm32f373/cec/
cr.rs
