stm32f3_staging/stm32f373/
can.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    mcr: MCR,
6    msr: MSR,
7    tsr: TSR,
8    rfr: [RFR; 2],
9    ier: IER,
10    esr: ESR,
11    btr: BTR,
12    _reserved7: [u8; 0x0160],
13    tx: [TX; 3],
14    rx: [RX; 2],
15    _reserved9: [u8; 0x30],
16    fmr: FMR,
17    fm1r: FM1R,
18    _reserved11: [u8; 0x04],
19    fs1r: FS1R,
20    _reserved12: [u8; 0x04],
21    ffa1r: FFA1R,
22    _reserved13: [u8; 0x04],
23    fa1r: FA1R,
24    _reserved14: [u8; 0x20],
25    fb: [FB; 28],
26}
27impl RegisterBlock {
28    ///0x00 - master control register
29    #[inline(always)]
30    pub const fn mcr(&self) -> &MCR {
31        &self.mcr
32    }
33    ///0x04 - master status register
34    #[inline(always)]
35    pub const fn msr(&self) -> &MSR {
36        &self.msr
37    }
38    ///0x08 - transmit status register
39    #[inline(always)]
40    pub const fn tsr(&self) -> &TSR {
41        &self.tsr
42    }
43    ///0x0c..0x14 - receive FIFO %s register
44    #[inline(always)]
45    pub const fn rfr(&self, n: usize) -> &RFR {
46        &self.rfr[n]
47    }
48    ///Iterator for array of:
49    ///0x0c..0x14 - receive FIFO %s register
50    #[inline(always)]
51    pub fn rfr_iter(&self) -> impl Iterator<Item = &RFR> {
52        self.rfr.iter()
53    }
54    ///0x0c - receive FIFO 0 register
55    #[inline(always)]
56    pub const fn rf0r(&self) -> &RFR {
57        self.rfr(0)
58    }
59    ///0x10 - receive FIFO 1 register
60    #[inline(always)]
61    pub const fn rf1r(&self) -> &RFR {
62        self.rfr(1)
63    }
64    ///0x14 - interrupt enable register
65    #[inline(always)]
66    pub const fn ier(&self) -> &IER {
67        &self.ier
68    }
69    ///0x18 - error status register
70    #[inline(always)]
71    pub const fn esr(&self) -> &ESR {
72        &self.esr
73    }
74    ///0x1c - bit timing register
75    #[inline(always)]
76    pub const fn btr(&self) -> &BTR {
77        &self.btr
78    }
79    ///0x180..0x1b0 - CAN Transmit cluster
80    #[inline(always)]
81    pub const fn tx(&self, n: usize) -> &TX {
82        &self.tx[n]
83    }
84    ///Iterator for array of:
85    ///0x180..0x1b0 - CAN Transmit cluster
86    #[inline(always)]
87    pub fn tx_iter(&self) -> impl Iterator<Item = &TX> {
88        self.tx.iter()
89    }
90    ///0x1b0..0x1d0 - CAN Receive cluster
91    #[inline(always)]
92    pub const fn rx(&self, n: usize) -> &RX {
93        &self.rx[n]
94    }
95    ///Iterator for array of:
96    ///0x1b0..0x1d0 - CAN Receive cluster
97    #[inline(always)]
98    pub fn rx_iter(&self) -> impl Iterator<Item = &RX> {
99        self.rx.iter()
100    }
101    ///0x200 - filter master register
102    #[inline(always)]
103    pub const fn fmr(&self) -> &FMR {
104        &self.fmr
105    }
106    ///0x204 - filter mode register
107    #[inline(always)]
108    pub const fn fm1r(&self) -> &FM1R {
109        &self.fm1r
110    }
111    ///0x20c - filter scale register
112    #[inline(always)]
113    pub const fn fs1r(&self) -> &FS1R {
114        &self.fs1r
115    }
116    ///0x214 - filter FIFO assignment register
117    #[inline(always)]
118    pub const fn ffa1r(&self) -> &FFA1R {
119        &self.ffa1r
120    }
121    ///0x21c - CAN filter activation register
122    #[inline(always)]
123    pub const fn fa1r(&self) -> &FA1R {
124        &self.fa1r
125    }
126    ///0x240..0x320 - CAN Filter Bank cluster
127    #[inline(always)]
128    pub const fn fb(&self, n: usize) -> &FB {
129        &self.fb[n]
130    }
131    ///Iterator for array of:
132    ///0x240..0x320 - CAN Filter Bank cluster
133    #[inline(always)]
134    pub fn fb_iter(&self) -> impl Iterator<Item = &FB> {
135        self.fb.iter()
136    }
137}
138/**MCR (rw) register accessor: master control register
139
140You can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
141
142See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:MCR)
143
144For information about available fields see [`mod@mcr`]
145module*/
146pub type MCR = crate::Reg<mcr::MCRrs>;
147///master control register
148pub mod mcr;
149/**MSR (rw) register accessor: master status register
150
151You can [`read`](crate::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
152
153See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:MSR)
154
155For information about available fields see [`mod@msr`]
156module*/
157pub type MSR = crate::Reg<msr::MSRrs>;
158///master status register
159pub mod msr;
160/**TSR (rw) register accessor: transmit status register
161
162You can [`read`](crate::Reg::read) this register and get [`tsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
163
164See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:TSR)
165
166For information about available fields see [`mod@tsr`]
167module*/
168pub type TSR = crate::Reg<tsr::TSRrs>;
169///transmit status register
170pub mod tsr;
171/**RFR (rw) register accessor: receive FIFO %s register
172
173You can [`read`](crate::Reg::read) this register and get [`rfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
174
175See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:RF[0]R)
176
177For information about available fields see [`mod@rfr`]
178module*/
179pub type RFR = crate::Reg<rfr::RFRrs>;
180///receive FIFO %s register
181pub mod rfr;
182/**IER (rw) register accessor: interrupt enable register
183
184You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
185
186See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:IER)
187
188For information about available fields see [`mod@ier`]
189module*/
190pub type IER = crate::Reg<ier::IERrs>;
191///interrupt enable register
192pub mod ier;
193/**ESR (rw) register accessor: error status register
194
195You can [`read`](crate::Reg::read) this register and get [`esr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
196
197See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:ESR)
198
199For information about available fields see [`mod@esr`]
200module*/
201pub type ESR = crate::Reg<esr::ESRrs>;
202///error status register
203pub mod esr;
204/**BTR (rw) register accessor: bit timing register
205
206You can [`read`](crate::Reg::read) this register and get [`btr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
207
208See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:BTR)
209
210For information about available fields see [`mod@btr`]
211module*/
212pub type BTR = crate::Reg<btr::BTRrs>;
213///bit timing register
214pub mod btr;
215///CAN Transmit cluster
216pub use self::tx::TX;
217///Cluster
218///CAN Transmit cluster
219pub mod tx;
220///CAN Receive cluster
221pub use self::rx::RX;
222///Cluster
223///CAN Receive cluster
224pub mod rx;
225/**FMR (rw) register accessor: filter master register
226
227You can [`read`](crate::Reg::read) this register and get [`fmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
228
229See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:FMR)
230
231For information about available fields see [`mod@fmr`]
232module*/
233pub type FMR = crate::Reg<fmr::FMRrs>;
234///filter master register
235pub mod fmr;
236/**FM1R (rw) register accessor: filter mode register
237
238You can [`read`](crate::Reg::read) this register and get [`fm1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fm1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
239
240See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:FM1R)
241
242For information about available fields see [`mod@fm1r`]
243module*/
244pub type FM1R = crate::Reg<fm1r::FM1Rrs>;
245///filter mode register
246pub mod fm1r;
247/**FS1R (rw) register accessor: filter scale register
248
249You can [`read`](crate::Reg::read) this register and get [`fs1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fs1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
250
251See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:FS1R)
252
253For information about available fields see [`mod@fs1r`]
254module*/
255pub type FS1R = crate::Reg<fs1r::FS1Rrs>;
256///filter scale register
257pub mod fs1r;
258/**FFA1R (rw) register accessor: filter FIFO assignment register
259
260You can [`read`](crate::Reg::read) this register and get [`ffa1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ffa1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
261
262See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:FFA1R)
263
264For information about available fields see [`mod@ffa1r`]
265module*/
266pub type FFA1R = crate::Reg<ffa1r::FFA1Rrs>;
267///filter FIFO assignment register
268pub mod ffa1r;
269/**FA1R (rw) register accessor: CAN filter activation register
270
271You can [`read`](crate::Reg::read) this register and get [`fa1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fa1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
272
273See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#CAN:FA1R)
274
275For information about available fields see [`mod@fa1r`]
276module*/
277pub type FA1R = crate::Reg<fa1r::FA1Rrs>;
278///CAN filter activation register
279pub mod fa1r;
280///CAN Filter Bank cluster
281pub use self::fb::FB;
282///Cluster
283///CAN Filter Bank cluster
284pub mod fb;
stm32f3_staging/stm32f373/can.rs

stm32f3_staging/stm32f373/
can.rs
