stm32f3_staging/stm32f303/tsc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `TSCE` reader - Touch sensing controller enable
6pub type TSCE_R = crate::BitReader;
7///Field `TSCE` writer - Touch sensing controller enable
8pub type TSCE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `START` reader - Start a new acquisition
10pub type START_R = crate::BitReader;
11///Field `START` writer - Start a new acquisition
12pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `AM` reader - Acquisition mode
14pub type AM_R = crate::BitReader;
15///Field `AM` writer - Acquisition mode
16pub type AM_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `SYNCPOL` reader - Synchronization pin polarity
18pub type SYNCPOL_R = crate::BitReader;
19///Field `SYNCPOL` writer - Synchronization pin polarity
20pub type SYNCPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `IODEF` reader - I/O Default mode
22pub type IODEF_R = crate::BitReader;
23///Field `IODEF` writer - I/O Default mode
24pub type IODEF_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `MCV` reader - Max count value
26pub type MCV_R = crate::FieldReader;
27///Field `MCV` writer - Max count value
28pub type MCV_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29///Field `PGPSC` reader - pulse generator prescaler
30pub type PGPSC_R = crate::FieldReader;
31///Field `PGPSC` writer - pulse generator prescaler
32pub type PGPSC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33///Field `SSPSC` reader - Spread spectrum prescaler
34pub type SSPSC_R = crate::BitReader;
35///Field `SSPSC` writer - Spread spectrum prescaler
36pub type SSPSC_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `SSE` reader - Spread spectrum enable
38pub type SSE_R = crate::BitReader;
39///Field `SSE` writer - Spread spectrum enable
40pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `SSD` reader - Spread spectrum deviation
42pub type SSD_R = crate::FieldReader;
43///Field `SSD` writer - Spread spectrum deviation
44pub type SSD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
45///Field `CTPL` reader - Charge transfer pulse low
46pub type CTPL_R = crate::FieldReader;
47///Field `CTPL` writer - Charge transfer pulse low
48pub type CTPL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
49///Field `CTPH` reader - Charge transfer pulse high
50pub type CTPH_R = crate::FieldReader;
51///Field `CTPH` writer - Charge transfer pulse high
52pub type CTPH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
53impl R {
54    ///Bit 0 - Touch sensing controller enable
55    #[inline(always)]
56    pub fn tsce(&self) -> TSCE_R {
57        TSCE_R::new((self.bits & 1) != 0)
58    }
59    ///Bit 1 - Start a new acquisition
60    #[inline(always)]
61    pub fn start(&self) -> START_R {
62        START_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    ///Bit 2 - Acquisition mode
65    #[inline(always)]
66    pub fn am(&self) -> AM_R {
67        AM_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    ///Bit 3 - Synchronization pin polarity
70    #[inline(always)]
71    pub fn syncpol(&self) -> SYNCPOL_R {
72        SYNCPOL_R::new(((self.bits >> 3) & 1) != 0)
73    }
74    ///Bit 4 - I/O Default mode
75    #[inline(always)]
76    pub fn iodef(&self) -> IODEF_R {
77        IODEF_R::new(((self.bits >> 4) & 1) != 0)
78    }
79    ///Bits 5:7 - Max count value
80    #[inline(always)]
81    pub fn mcv(&self) -> MCV_R {
82        MCV_R::new(((self.bits >> 5) & 7) as u8)
83    }
84    ///Bits 12:14 - pulse generator prescaler
85    #[inline(always)]
86    pub fn pgpsc(&self) -> PGPSC_R {
87        PGPSC_R::new(((self.bits >> 12) & 7) as u8)
88    }
89    ///Bit 15 - Spread spectrum prescaler
90    #[inline(always)]
91    pub fn sspsc(&self) -> SSPSC_R {
92        SSPSC_R::new(((self.bits >> 15) & 1) != 0)
93    }
94    ///Bit 16 - Spread spectrum enable
95    #[inline(always)]
96    pub fn sse(&self) -> SSE_R {
97        SSE_R::new(((self.bits >> 16) & 1) != 0)
98    }
99    ///Bits 17:23 - Spread spectrum deviation
100    #[inline(always)]
101    pub fn ssd(&self) -> SSD_R {
102        SSD_R::new(((self.bits >> 17) & 0x7f) as u8)
103    }
104    ///Bits 24:27 - Charge transfer pulse low
105    #[inline(always)]
106    pub fn ctpl(&self) -> CTPL_R {
107        CTPL_R::new(((self.bits >> 24) & 0x0f) as u8)
108    }
109    ///Bits 28:31 - Charge transfer pulse high
110    #[inline(always)]
111    pub fn ctph(&self) -> CTPH_R {
112        CTPH_R::new(((self.bits >> 28) & 0x0f) as u8)
113    }
114}
115impl core::fmt::Debug for R {
116    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
117        f.debug_struct("CR")
118            .field("ctph", &self.ctph())
119            .field("ctpl", &self.ctpl())
120            .field("ssd", &self.ssd())
121            .field("sse", &self.sse())
122            .field("sspsc", &self.sspsc())
123            .field("pgpsc", &self.pgpsc())
124            .field("mcv", &self.mcv())
125            .field("iodef", &self.iodef())
126            .field("syncpol", &self.syncpol())
127            .field("am", &self.am())
128            .field("start", &self.start())
129            .field("tsce", &self.tsce())
130            .finish()
131    }
132}
133impl W {
134    ///Bit 0 - Touch sensing controller enable
135    #[inline(always)]
136    pub fn tsce(&mut self) -> TSCE_W<CRrs> {
137        TSCE_W::new(self, 0)
138    }
139    ///Bit 1 - Start a new acquisition
140    #[inline(always)]
141    pub fn start(&mut self) -> START_W<CRrs> {
142        START_W::new(self, 1)
143    }
144    ///Bit 2 - Acquisition mode
145    #[inline(always)]
146    pub fn am(&mut self) -> AM_W<CRrs> {
147        AM_W::new(self, 2)
148    }
149    ///Bit 3 - Synchronization pin polarity
150    #[inline(always)]
151    pub fn syncpol(&mut self) -> SYNCPOL_W<CRrs> {
152        SYNCPOL_W::new(self, 3)
153    }
154    ///Bit 4 - I/O Default mode
155    #[inline(always)]
156    pub fn iodef(&mut self) -> IODEF_W<CRrs> {
157        IODEF_W::new(self, 4)
158    }
159    ///Bits 5:7 - Max count value
160    #[inline(always)]
161    pub fn mcv(&mut self) -> MCV_W<CRrs> {
162        MCV_W::new(self, 5)
163    }
164    ///Bits 12:14 - pulse generator prescaler
165    #[inline(always)]
166    pub fn pgpsc(&mut self) -> PGPSC_W<CRrs> {
167        PGPSC_W::new(self, 12)
168    }
169    ///Bit 15 - Spread spectrum prescaler
170    #[inline(always)]
171    pub fn sspsc(&mut self) -> SSPSC_W<CRrs> {
172        SSPSC_W::new(self, 15)
173    }
174    ///Bit 16 - Spread spectrum enable
175    #[inline(always)]
176    pub fn sse(&mut self) -> SSE_W<CRrs> {
177        SSE_W::new(self, 16)
178    }
179    ///Bits 17:23 - Spread spectrum deviation
180    #[inline(always)]
181    pub fn ssd(&mut self) -> SSD_W<CRrs> {
182        SSD_W::new(self, 17)
183    }
184    ///Bits 24:27 - Charge transfer pulse low
185    #[inline(always)]
186    pub fn ctpl(&mut self) -> CTPL_W<CRrs> {
187        CTPL_W::new(self, 24)
188    }
189    ///Bits 28:31 - Charge transfer pulse high
190    #[inline(always)]
191    pub fn ctph(&mut self) -> CTPH_W<CRrs> {
192        CTPH_W::new(self, 28)
193    }
194}
195/**control register
196
197You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
198
199See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TSC:CR)*/
200pub struct CRrs;
201impl crate::RegisterSpec for CRrs {
202    type Ux = u32;
203}
204///`read()` method returns [`cr::R`](R) reader structure
205impl crate::Readable for CRrs {}
206///`write(|w| ..)` method takes [`cr::W`](W) writer structure
207impl crate::Writable for CRrs {
208    type Safety = crate::Unsafe;
209    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
210    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
211}
212///`reset()` method sets CR to value 0
213impl crate::Resettable for CRrs {
214    const RESET_VALUE: u32 = 0;
215}
stm32f3_staging/stm32f303/tsc/cr.rs

stm32f3_staging/stm32f303/tsc/
cr.rs
