stm32f3_staging/stm32f303/
tim16.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    _reserved2: [u8; 0x04],
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_5_ccmr1: [u8; 0x04],
12    _reserved6: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 1],
19    _reserved12: [u8; 0x0c],
20    bdtr: BDTR,
21    dcr: DCR,
22    dmar: DMAR,
23    or: OR,
24}
25impl RegisterBlock {
26    ///0x00 - control register 1
27    #[inline(always)]
28    pub const fn cr1(&self) -> &CR1 {
29        &self.cr1
30    }
31    ///0x04 - control register 2
32    #[inline(always)]
33    pub const fn cr2(&self) -> &CR2 {
34        &self.cr2
35    }
36    ///0x0c - DMA/Interrupt enable register
37    #[inline(always)]
38    pub const fn dier(&self) -> &DIER {
39        &self.dier
40    }
41    ///0x10 - status register
42    #[inline(always)]
43    pub const fn sr(&self) -> &SR {
44        &self.sr
45    }
46    ///0x14 - event generation register
47    #[inline(always)]
48    pub const fn egr(&self) -> &EGR {
49        &self.egr
50    }
51    ///0x18 - capture/compare mode register 1 (input mode)
52    #[inline(always)]
53    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
54        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
55    }
56    ///0x18 - capture/compare mode register (output mode)
57    #[inline(always)]
58    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
59        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
60    }
61    ///0x20 - capture/compare enable register
62    #[inline(always)]
63    pub const fn ccer(&self) -> &CCER {
64        &self.ccer
65    }
66    ///0x24 - counter
67    #[inline(always)]
68    pub const fn cnt(&self) -> &CNT {
69        &self.cnt
70    }
71    ///0x28 - prescaler
72    #[inline(always)]
73    pub const fn psc(&self) -> &PSC {
74        &self.psc
75    }
76    ///0x2c - auto-reload register
77    #[inline(always)]
78    pub const fn arr(&self) -> &ARR {
79        &self.arr
80    }
81    ///0x30 - repetition counter register
82    #[inline(always)]
83    pub const fn rcr(&self) -> &RCR {
84        &self.rcr
85    }
86    ///0x34 - capture/compare register
87    ///
88    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
89    #[inline(always)]
90    pub const fn ccr(&self, n: usize) -> &CCR {
91        &self.ccr[n]
92    }
93    ///Iterator for array of:
94    ///0x34 - capture/compare register
95    #[inline(always)]
96    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
97        self.ccr.iter()
98    }
99    ///0x34 - capture/compare register
100    #[inline(always)]
101    pub const fn ccr1(&self) -> &CCR {
102        self.ccr(0)
103    }
104    ///0x44 - break and dead-time register
105    #[inline(always)]
106    pub const fn bdtr(&self) -> &BDTR {
107        &self.bdtr
108    }
109    ///0x48 - DMA control register
110    #[inline(always)]
111    pub const fn dcr(&self) -> &DCR {
112        &self.dcr
113    }
114    ///0x4c - DMA address for full transfer
115    #[inline(always)]
116    pub const fn dmar(&self) -> &DMAR {
117        &self.dmar
118    }
119    ///0x50 - option register
120    #[inline(always)]
121    pub const fn or(&self) -> &OR {
122        &self.or
123    }
124}
125/**CR1 (rw) register accessor: control register 1
126
127You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
128
129See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CR1)
130
131For information about available fields see [`mod@cr1`]
132module*/
133pub type CR1 = crate::Reg<cr1::CR1rs>;
134///control register 1
135pub mod cr1;
136/**CR2 (rw) register accessor: control register 2
137
138You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
139
140See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CR2)
141
142For information about available fields see [`mod@cr2`]
143module*/
144pub type CR2 = crate::Reg<cr2::CR2rs>;
145///control register 2
146pub mod cr2;
147/**DIER (rw) register accessor: DMA/Interrupt enable register
148
149You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
150
151See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:DIER)
152
153For information about available fields see [`mod@dier`]
154module*/
155pub type DIER = crate::Reg<dier::DIERrs>;
156///DMA/Interrupt enable register
157pub mod dier;
158/**SR (rw) register accessor: status register
159
160You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:SR)
163
164For information about available fields see [`mod@sr`]
165module*/
166pub type SR = crate::Reg<sr::SRrs>;
167///status register
168pub mod sr;
169/**EGR (w) register accessor: event generation register
170
171You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
172
173See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:EGR)
174
175For information about available fields see [`mod@egr`]
176module*/
177pub type EGR = crate::Reg<egr::EGRrs>;
178///event generation register
179pub mod egr;
180/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
181
182You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CCMR1_Output)
185
186For information about available fields see [`mod@ccmr1_output`]
187module*/
188#[doc(alias = "CCMR1_Output")]
189pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
190///capture/compare mode register (output mode)
191pub mod ccmr1_output;
192/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
193
194You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
195
196See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CCMR1_Input)
197
198For information about available fields see [`mod@ccmr1_input`]
199module*/
200#[doc(alias = "CCMR1_Input")]
201pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
202///capture/compare mode register 1 (input mode)
203pub mod ccmr1_input;
204/**CCER (rw) register accessor: capture/compare enable register
205
206You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
207
208See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CCER)
209
210For information about available fields see [`mod@ccer`]
211module*/
212pub type CCER = crate::Reg<ccer::CCERrs>;
213///capture/compare enable register
214pub mod ccer;
215/**CNT (rw) register accessor: counter
216
217You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
218
219See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CNT)
220
221For information about available fields see [`mod@cnt`]
222module*/
223pub type CNT = crate::Reg<cnt::CNTrs>;
224///counter
225pub mod cnt;
226/**PSC (rw) register accessor: prescaler
227
228You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
229
230See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:PSC)
231
232For information about available fields see [`mod@psc`]
233module*/
234pub type PSC = crate::Reg<psc::PSCrs>;
235///prescaler
236pub mod psc;
237/**ARR (rw) register accessor: auto-reload register
238
239You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
240
241See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:ARR)
242
243For information about available fields see [`mod@arr`]
244module*/
245pub type ARR = crate::Reg<arr::ARRrs>;
246///auto-reload register
247pub mod arr;
248/**RCR (rw) register accessor: repetition counter register
249
250You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
251
252See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:RCR)
253
254For information about available fields see [`mod@rcr`]
255module*/
256pub type RCR = crate::Reg<rcr::RCRrs>;
257///repetition counter register
258pub mod rcr;
259/**CCR (rw) register accessor: capture/compare register
260
261You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
262
263See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:CCR[1])
264
265For information about available fields see [`mod@ccr`]
266module*/
267pub type CCR = crate::Reg<ccr::CCRrs>;
268///capture/compare register
269pub mod ccr;
270/**BDTR (rw) register accessor: break and dead-time register
271
272You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
273
274See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:BDTR)
275
276For information about available fields see [`mod@bdtr`]
277module*/
278pub type BDTR = crate::Reg<bdtr::BDTRrs>;
279///break and dead-time register
280pub mod bdtr;
281/**DCR (rw) register accessor: DMA control register
282
283You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
284
285See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:DCR)
286
287For information about available fields see [`mod@dcr`]
288module*/
289pub type DCR = crate::Reg<dcr::DCRrs>;
290///DMA control register
291pub mod dcr;
292/**DMAR (rw) register accessor: DMA address for full transfer
293
294You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:DMAR)
297
298For information about available fields see [`mod@dmar`]
299module*/
300pub type DMAR = crate::Reg<dmar::DMARrs>;
301///DMA address for full transfer
302pub mod dmar;
303/**OR (rw) register accessor: option register
304
305You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
306
307See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16:OR)
308
309For information about available fields see [`mod@or`]
310module*/
311pub type OR = crate::Reg<or::ORrs>;
312///option register
313pub mod or;
stm32f3_staging/stm32f303/tim16.rs

stm32f3_staging/stm32f303/
tim16.rs
