stm32f3_staging/stm32f303/adc1/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**ADEN
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ADENR {
11    ///0: ADC disabled
12    Disabled = 0,
13    ///1: ADC enabled
14    Enabled = 1,
15}
16impl From<ADENR> for bool {
17    #[inline(always)]
18    fn from(variant: ADENR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ADEN` reader - ADEN
23pub type ADEN_R = crate::BitReader<ADENR>;
24impl ADEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ADENR {
28        match self.bits {
29            false => ADENR::Disabled,
30            true => ADENR::Enabled,
31        }
32    }
33    ///ADC disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ADENR::Disabled
37    }
38    ///ADC enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ADENR::Enabled
42    }
43}
44/**ADEN
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum ADENW {
50    ///1: Enable the ADC
51    Enabled = 1,
52}
53impl From<ADENW> for bool {
54    #[inline(always)]
55    fn from(variant: ADENW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `ADEN` writer - ADEN
60pub type ADEN_W<'a, REG> = crate::BitWriter1S<'a, REG, ADENW>;
61impl<'a, REG> ADEN_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Enable the ADC
66    #[inline(always)]
67    pub fn enabled(self) -> &'a mut crate::W<REG> {
68        self.variant(ADENW::Enabled)
69    }
70}
71/**ADDIS
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum ADDISR {
77    ///0: No disable command active
78    NotDisabling = 0,
79    ///1: ADC disabling
80    Disabling = 1,
81}
82impl From<ADDISR> for bool {
83    #[inline(always)]
84    fn from(variant: ADDISR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `ADDIS` reader - ADDIS
89pub type ADDIS_R = crate::BitReader<ADDISR>;
90impl ADDIS_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> ADDISR {
94        match self.bits {
95            false => ADDISR::NotDisabling,
96            true => ADDISR::Disabling,
97        }
98    }
99    ///No disable command active
100    #[inline(always)]
101    pub fn is_not_disabling(&self) -> bool {
102        *self == ADDISR::NotDisabling
103    }
104    ///ADC disabling
105    #[inline(always)]
106    pub fn is_disabling(&self) -> bool {
107        *self == ADDISR::Disabling
108    }
109}
110/**ADDIS
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum ADDISW {
116    ///1: Disable the ADC
117    Disable = 1,
118}
119impl From<ADDISW> for bool {
120    #[inline(always)]
121    fn from(variant: ADDISW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `ADDIS` writer - ADDIS
126pub type ADDIS_W<'a, REG> = crate::BitWriter1S<'a, REG, ADDISW>;
127impl<'a, REG> ADDIS_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Disable the ADC
132    #[inline(always)]
133    pub fn disable(self) -> &'a mut crate::W<REG> {
134        self.variant(ADDISW::Disable)
135    }
136}
137/**ADSTART
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum ADSTARTR {
143    ///0: No conversion ongoing
144    NotActive = 0,
145    ///1: ADC operating and may be converting
146    Active = 1,
147}
148impl From<ADSTARTR> for bool {
149    #[inline(always)]
150    fn from(variant: ADSTARTR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `ADSTART` reader - ADSTART
155pub type ADSTART_R = crate::BitReader<ADSTARTR>;
156impl ADSTART_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> ADSTARTR {
160        match self.bits {
161            false => ADSTARTR::NotActive,
162            true => ADSTARTR::Active,
163        }
164    }
165    ///No conversion ongoing
166    #[inline(always)]
167    pub fn is_not_active(&self) -> bool {
168        *self == ADSTARTR::NotActive
169    }
170    ///ADC operating and may be converting
171    #[inline(always)]
172    pub fn is_active(&self) -> bool {
173        *self == ADSTARTR::Active
174    }
175}
176/**ADSTART
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum ADSTARTW {
182    ///1: Start the ADC conversion (may be delayed for hardware triggers)
183    StartConversion = 1,
184}
185impl From<ADSTARTW> for bool {
186    #[inline(always)]
187    fn from(variant: ADSTARTW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `ADSTART` writer - ADSTART
192pub type ADSTART_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTARTW>;
193impl<'a, REG> ADSTART_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Start the ADC conversion (may be delayed for hardware triggers)
198    #[inline(always)]
199    pub fn start_conversion(self) -> &'a mut crate::W<REG> {
200        self.variant(ADSTARTW::StartConversion)
201    }
202}
203///Field `JADSTART` reader - JADSTART
204pub use ADSTART_R as JADSTART_R;
205///Field `JADSTART` writer - JADSTART
206pub use ADSTART_W as JADSTART_W;
207/**ADSTP
208
209Value on reset: 0*/
210#[cfg_attr(feature = "defmt", derive(defmt::Format))]
211#[derive(Clone, Copy, Debug, PartialEq, Eq)]
212pub enum ADSTPR {
213    ///0: No stop command active
214    NotStopping = 0,
215    ///1: ADC stopping conversion
216    Stopping = 1,
217}
218impl From<ADSTPR> for bool {
219    #[inline(always)]
220    fn from(variant: ADSTPR) -> Self {
221        variant as u8 != 0
222    }
223}
224///Field `ADSTP` reader - ADSTP
225pub type ADSTP_R = crate::BitReader<ADSTPR>;
226impl ADSTP_R {
227    ///Get enumerated values variant
228    #[inline(always)]
229    pub const fn variant(&self) -> ADSTPR {
230        match self.bits {
231            false => ADSTPR::NotStopping,
232            true => ADSTPR::Stopping,
233        }
234    }
235    ///No stop command active
236    #[inline(always)]
237    pub fn is_not_stopping(&self) -> bool {
238        *self == ADSTPR::NotStopping
239    }
240    ///ADC stopping conversion
241    #[inline(always)]
242    pub fn is_stopping(&self) -> bool {
243        *self == ADSTPR::Stopping
244    }
245}
246/**ADSTP
247
248Value on reset: 0*/
249#[cfg_attr(feature = "defmt", derive(defmt::Format))]
250#[derive(Clone, Copy, Debug, PartialEq, Eq)]
251pub enum ADSTPW {
252    ///1: Stop the active conversion
253    StopConversion = 1,
254}
255impl From<ADSTPW> for bool {
256    #[inline(always)]
257    fn from(variant: ADSTPW) -> Self {
258        variant as u8 != 0
259    }
260}
261///Field `ADSTP` writer - ADSTP
262pub type ADSTP_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTPW>;
263impl<'a, REG> ADSTP_W<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    ///Stop the active conversion
268    #[inline(always)]
269    pub fn stop_conversion(self) -> &'a mut crate::W<REG> {
270        self.variant(ADSTPW::StopConversion)
271    }
272}
273///Field `JADSTP` reader - JADSTP
274pub use ADSTP_R as JADSTP_R;
275///Field `JADSTP` writer - JADSTP
276pub use ADSTP_W as JADSTP_W;
277/**ADVREGEN
278
279Value on reset: 0*/
280#[cfg_attr(feature = "defmt", derive(defmt::Format))]
281#[derive(Clone, Copy, Debug, PartialEq, Eq)]
282#[repr(u8)]
283pub enum ADVREGEN {
284    ///0: Intermediate state required when moving the ADC voltage regulator between states
285    Intermediate = 0,
286    ///1: ADC voltage regulator enabled
287    Enabled = 1,
288    ///2: ADC voltage regulator disabled
289    Disabled = 2,
290}
291impl From<ADVREGEN> for u8 {
292    #[inline(always)]
293    fn from(variant: ADVREGEN) -> Self {
294        variant as _
295    }
296}
297impl crate::FieldSpec for ADVREGEN {
298    type Ux = u8;
299}
300impl crate::IsEnum for ADVREGEN {}
301///Field `ADVREGEN` reader - ADVREGEN
302pub type ADVREGEN_R = crate::FieldReader<ADVREGEN>;
303impl ADVREGEN_R {
304    ///Get enumerated values variant
305    #[inline(always)]
306    pub const fn variant(&self) -> Option<ADVREGEN> {
307        match self.bits {
308            0 => Some(ADVREGEN::Intermediate),
309            1 => Some(ADVREGEN::Enabled),
310            2 => Some(ADVREGEN::Disabled),
311            _ => None,
312        }
313    }
314    ///Intermediate state required when moving the ADC voltage regulator between states
315    #[inline(always)]
316    pub fn is_intermediate(&self) -> bool {
317        *self == ADVREGEN::Intermediate
318    }
319    ///ADC voltage regulator enabled
320    #[inline(always)]
321    pub fn is_enabled(&self) -> bool {
322        *self == ADVREGEN::Enabled
323    }
324    ///ADC voltage regulator disabled
325    #[inline(always)]
326    pub fn is_disabled(&self) -> bool {
327        *self == ADVREGEN::Disabled
328    }
329}
330///Field `ADVREGEN` writer - ADVREGEN
331pub type ADVREGEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADVREGEN>;
332impl<'a, REG> ADVREGEN_W<'a, REG>
333where
334    REG: crate::Writable + crate::RegisterSpec,
335    REG::Ux: From<u8>,
336{
337    ///Intermediate state required when moving the ADC voltage regulator between states
338    #[inline(always)]
339    pub fn intermediate(self) -> &'a mut crate::W<REG> {
340        self.variant(ADVREGEN::Intermediate)
341    }
342    ///ADC voltage regulator enabled
343    #[inline(always)]
344    pub fn enabled(self) -> &'a mut crate::W<REG> {
345        self.variant(ADVREGEN::Enabled)
346    }
347    ///ADC voltage regulator disabled
348    #[inline(always)]
349    pub fn disabled(self) -> &'a mut crate::W<REG> {
350        self.variant(ADVREGEN::Disabled)
351    }
352}
353/**ADCALDIF
354
355Value on reset: 0*/
356#[cfg_attr(feature = "defmt", derive(defmt::Format))]
357#[derive(Clone, Copy, Debug, PartialEq, Eq)]
358pub enum ADCALDIF {
359    ///0: Calibration for single-ended mode
360    SingleEnded = 0,
361    ///1: Calibration for differential mode
362    Differential = 1,
363}
364impl From<ADCALDIF> for bool {
365    #[inline(always)]
366    fn from(variant: ADCALDIF) -> Self {
367        variant as u8 != 0
368    }
369}
370///Field `ADCALDIF` reader - ADCALDIF
371pub type ADCALDIF_R = crate::BitReader<ADCALDIF>;
372impl ADCALDIF_R {
373    ///Get enumerated values variant
374    #[inline(always)]
375    pub const fn variant(&self) -> ADCALDIF {
376        match self.bits {
377            false => ADCALDIF::SingleEnded,
378            true => ADCALDIF::Differential,
379        }
380    }
381    ///Calibration for single-ended mode
382    #[inline(always)]
383    pub fn is_single_ended(&self) -> bool {
384        *self == ADCALDIF::SingleEnded
385    }
386    ///Calibration for differential mode
387    #[inline(always)]
388    pub fn is_differential(&self) -> bool {
389        *self == ADCALDIF::Differential
390    }
391}
392///Field `ADCALDIF` writer - ADCALDIF
393pub type ADCALDIF_W<'a, REG> = crate::BitWriter<'a, REG, ADCALDIF>;
394impl<'a, REG> ADCALDIF_W<'a, REG>
395where
396    REG: crate::Writable + crate::RegisterSpec,
397{
398    ///Calibration for single-ended mode
399    #[inline(always)]
400    pub fn single_ended(self) -> &'a mut crate::W<REG> {
401        self.variant(ADCALDIF::SingleEnded)
402    }
403    ///Calibration for differential mode
404    #[inline(always)]
405    pub fn differential(self) -> &'a mut crate::W<REG> {
406        self.variant(ADCALDIF::Differential)
407    }
408}
409/**ADCAL
410
411Value on reset: 0*/
412#[cfg_attr(feature = "defmt", derive(defmt::Format))]
413#[derive(Clone, Copy, Debug, PartialEq, Eq)]
414pub enum ADCALR {
415    ///0: ADC calibration either not yet performed or completed
416    NotCalibrating = 0,
417    ///1: ADC calibration in progress
418    Calibrating = 1,
419}
420impl From<ADCALR> for bool {
421    #[inline(always)]
422    fn from(variant: ADCALR) -> Self {
423        variant as u8 != 0
424    }
425}
426///Field `ADCAL` reader - ADCAL
427pub type ADCAL_R = crate::BitReader<ADCALR>;
428impl ADCAL_R {
429    ///Get enumerated values variant
430    #[inline(always)]
431    pub const fn variant(&self) -> ADCALR {
432        match self.bits {
433            false => ADCALR::NotCalibrating,
434            true => ADCALR::Calibrating,
435        }
436    }
437    ///ADC calibration either not yet performed or completed
438    #[inline(always)]
439    pub fn is_not_calibrating(&self) -> bool {
440        *self == ADCALR::NotCalibrating
441    }
442    ///ADC calibration in progress
443    #[inline(always)]
444    pub fn is_calibrating(&self) -> bool {
445        *self == ADCALR::Calibrating
446    }
447}
448/**ADCAL
449
450Value on reset: 0*/
451#[cfg_attr(feature = "defmt", derive(defmt::Format))]
452#[derive(Clone, Copy, Debug, PartialEq, Eq)]
453pub enum ADCALW {
454    ///1: Start the ADC calibration sequence
455    StartCalibration = 1,
456}
457impl From<ADCALW> for bool {
458    #[inline(always)]
459    fn from(variant: ADCALW) -> Self {
460        variant as u8 != 0
461    }
462}
463///Field `ADCAL` writer - ADCAL
464pub type ADCAL_W<'a, REG> = crate::BitWriter1S<'a, REG, ADCALW>;
465impl<'a, REG> ADCAL_W<'a, REG>
466where
467    REG: crate::Writable + crate::RegisterSpec,
468{
469    ///Start the ADC calibration sequence
470    #[inline(always)]
471    pub fn start_calibration(self) -> &'a mut crate::W<REG> {
472        self.variant(ADCALW::StartCalibration)
473    }
474}
475impl R {
476    ///Bit 0 - ADEN
477    #[inline(always)]
478    pub fn aden(&self) -> ADEN_R {
479        ADEN_R::new((self.bits & 1) != 0)
480    }
481    ///Bit 1 - ADDIS
482    #[inline(always)]
483    pub fn addis(&self) -> ADDIS_R {
484        ADDIS_R::new(((self.bits >> 1) & 1) != 0)
485    }
486    ///Bit 2 - ADSTART
487    #[inline(always)]
488    pub fn adstart(&self) -> ADSTART_R {
489        ADSTART_R::new(((self.bits >> 2) & 1) != 0)
490    }
491    ///Bit 3 - JADSTART
492    #[inline(always)]
493    pub fn jadstart(&self) -> JADSTART_R {
494        JADSTART_R::new(((self.bits >> 3) & 1) != 0)
495    }
496    ///Bit 4 - ADSTP
497    #[inline(always)]
498    pub fn adstp(&self) -> ADSTP_R {
499        ADSTP_R::new(((self.bits >> 4) & 1) != 0)
500    }
501    ///Bit 5 - JADSTP
502    #[inline(always)]
503    pub fn jadstp(&self) -> JADSTP_R {
504        JADSTP_R::new(((self.bits >> 5) & 1) != 0)
505    }
506    ///Bits 28:29 - ADVREGEN
507    #[inline(always)]
508    pub fn advregen(&self) -> ADVREGEN_R {
509        ADVREGEN_R::new(((self.bits >> 28) & 3) as u8)
510    }
511    ///Bit 30 - ADCALDIF
512    #[inline(always)]
513    pub fn adcaldif(&self) -> ADCALDIF_R {
514        ADCALDIF_R::new(((self.bits >> 30) & 1) != 0)
515    }
516    ///Bit 31 - ADCAL
517    #[inline(always)]
518    pub fn adcal(&self) -> ADCAL_R {
519        ADCAL_R::new(((self.bits >> 31) & 1) != 0)
520    }
521}
522impl core::fmt::Debug for R {
523    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
524        f.debug_struct("CR")
525            .field("adcal", &self.adcal())
526            .field("adcaldif", &self.adcaldif())
527            .field("advregen", &self.advregen())
528            .field("adstp", &self.adstp())
529            .field("jadstp", &self.jadstp())
530            .field("adstart", &self.adstart())
531            .field("jadstart", &self.jadstart())
532            .field("addis", &self.addis())
533            .field("aden", &self.aden())
534            .finish()
535    }
536}
537impl W {
538    ///Bit 0 - ADEN
539    #[inline(always)]
540    pub fn aden(&mut self) -> ADEN_W<CRrs> {
541        ADEN_W::new(self, 0)
542    }
543    ///Bit 1 - ADDIS
544    #[inline(always)]
545    pub fn addis(&mut self) -> ADDIS_W<CRrs> {
546        ADDIS_W::new(self, 1)
547    }
548    ///Bit 2 - ADSTART
549    #[inline(always)]
550    pub fn adstart(&mut self) -> ADSTART_W<CRrs> {
551        ADSTART_W::new(self, 2)
552    }
553    ///Bit 3 - JADSTART
554    #[inline(always)]
555    pub fn jadstart(&mut self) -> JADSTART_W<CRrs> {
556        JADSTART_W::new(self, 3)
557    }
558    ///Bit 4 - ADSTP
559    #[inline(always)]
560    pub fn adstp(&mut self) -> ADSTP_W<CRrs> {
561        ADSTP_W::new(self, 4)
562    }
563    ///Bit 5 - JADSTP
564    #[inline(always)]
565    pub fn jadstp(&mut self) -> JADSTP_W<CRrs> {
566        JADSTP_W::new(self, 5)
567    }
568    ///Bits 28:29 - ADVREGEN
569    #[inline(always)]
570    pub fn advregen(&mut self) -> ADVREGEN_W<CRrs> {
571        ADVREGEN_W::new(self, 28)
572    }
573    ///Bit 30 - ADCALDIF
574    #[inline(always)]
575    pub fn adcaldif(&mut self) -> ADCALDIF_W<CRrs> {
576        ADCALDIF_W::new(self, 30)
577    }
578    ///Bit 31 - ADCAL
579    #[inline(always)]
580    pub fn adcal(&mut self) -> ADCAL_W<CRrs> {
581        ADCAL_W::new(self, 31)
582    }
583}
584/**control register
585
586You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
587
588See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:CR)*/
589pub struct CRrs;
590impl crate::RegisterSpec for CRrs {
591    type Ux = u32;
592}
593///`read()` method returns [`cr::R`](R) reader structure
594impl crate::Readable for CRrs {}
595///`write(|w| ..)` method takes [`cr::W`](W) writer structure
596impl crate::Writable for CRrs {
597    type Safety = crate::Unsafe;
598    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
599    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_003f;
600}
601///`reset()` method sets CR to value 0
602impl crate::Resettable for CRrs {
603    const RESET_VALUE: u32 = 0;
604}
stm32f3_staging/stm32f303/adc1/cr.rs

stm32f3_staging/stm32f303/adc1/
cr.rs
