stm32f3_staging/stm32f302/
tim15.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved7: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 2],
19    _reserved13: [u8; 0x08],
20    bdtr: BDTR,
21    dcr: DCR,
22    dmar: DMAR,
23}
24impl RegisterBlock {
25    ///0x00 - control register 1
26    #[inline(always)]
27    pub const fn cr1(&self) -> &CR1 {
28        &self.cr1
29    }
30    ///0x04 - control register 2
31    #[inline(always)]
32    pub const fn cr2(&self) -> &CR2 {
33        &self.cr2
34    }
35    ///0x08 - slave mode control register
36    #[inline(always)]
37    pub const fn smcr(&self) -> &SMCR {
38        &self.smcr
39    }
40    ///0x0c - DMA/Interrupt enable register
41    #[inline(always)]
42    pub const fn dier(&self) -> &DIER {
43        &self.dier
44    }
45    ///0x10 - status register
46    #[inline(always)]
47    pub const fn sr(&self) -> &SR {
48        &self.sr
49    }
50    ///0x14 - event generation register
51    #[inline(always)]
52    pub const fn egr(&self) -> &EGR {
53        &self.egr
54    }
55    ///0x18 - capture/compare mode register 1 (input mode)
56    #[inline(always)]
57    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
58        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
59    }
60    ///0x18 - capture/compare mode register (output mode)
61    #[inline(always)]
62    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
64    }
65    ///0x20 - capture/compare enable register
66    #[inline(always)]
67    pub const fn ccer(&self) -> &CCER {
68        &self.ccer
69    }
70    ///0x24 - counter
71    #[inline(always)]
72    pub const fn cnt(&self) -> &CNT {
73        &self.cnt
74    }
75    ///0x28 - prescaler
76    #[inline(always)]
77    pub const fn psc(&self) -> &PSC {
78        &self.psc
79    }
80    ///0x2c - auto-reload register
81    #[inline(always)]
82    pub const fn arr(&self) -> &ARR {
83        &self.arr
84    }
85    ///0x30 - repetition counter register
86    #[inline(always)]
87    pub const fn rcr(&self) -> &RCR {
88        &self.rcr
89    }
90    ///0x34..0x3c - capture/compare register
91    ///
92    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
93    #[inline(always)]
94    pub const fn ccr(&self, n: usize) -> &CCR {
95        &self.ccr[n]
96    }
97    ///Iterator for array of:
98    ///0x34..0x3c - capture/compare register
99    #[inline(always)]
100    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
101        self.ccr.iter()
102    }
103    ///0x34 - capture/compare register
104    #[inline(always)]
105    pub const fn ccr1(&self) -> &CCR {
106        self.ccr(0)
107    }
108    ///0x38 - capture/compare register
109    #[inline(always)]
110    pub const fn ccr2(&self) -> &CCR {
111        self.ccr(1)
112    }
113    ///0x44 - break and dead-time register
114    #[inline(always)]
115    pub const fn bdtr(&self) -> &BDTR {
116        &self.bdtr
117    }
118    ///0x48 - DMA control register
119    #[inline(always)]
120    pub const fn dcr(&self) -> &DCR {
121        &self.dcr
122    }
123    ///0x4c - DMA address for full transfer
124    #[inline(always)]
125    pub const fn dmar(&self) -> &DMAR {
126        &self.dmar
127    }
128}
129/**CR1 (rw) register accessor: control register 1
130
131You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CR1)
134
135For information about available fields see [`mod@cr1`]
136module*/
137pub type CR1 = crate::Reg<cr1::CR1rs>;
138///control register 1
139pub mod cr1;
140/**CR2 (rw) register accessor: control register 2
141
142You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CR2)
145
146For information about available fields see [`mod@cr2`]
147module*/
148pub type CR2 = crate::Reg<cr2::CR2rs>;
149///control register 2
150pub mod cr2;
151/**SMCR (rw) register accessor: slave mode control register
152
153You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
154
155See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:SMCR)
156
157For information about available fields see [`mod@smcr`]
158module*/
159pub type SMCR = crate::Reg<smcr::SMCRrs>;
160///slave mode control register
161pub mod smcr;
162/**DIER (rw) register accessor: DMA/Interrupt enable register
163
164You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
165
166See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:DIER)
167
168For information about available fields see [`mod@dier`]
169module*/
170pub type DIER = crate::Reg<dier::DIERrs>;
171///DMA/Interrupt enable register
172pub mod dier;
173/**SR (rw) register accessor: status register
174
175You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
176
177See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:SR)
178
179For information about available fields see [`mod@sr`]
180module*/
181pub type SR = crate::Reg<sr::SRrs>;
182///status register
183pub mod sr;
184/**EGR (w) register accessor: event generation register
185
186You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
187
188See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:EGR)
189
190For information about available fields see [`mod@egr`]
191module*/
192pub type EGR = crate::Reg<egr::EGRrs>;
193///event generation register
194pub mod egr;
195/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
196
197You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
198
199See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CCMR1_Output)
200
201For information about available fields see [`mod@ccmr1_output`]
202module*/
203#[doc(alias = "CCMR1_Output")]
204pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
205///capture/compare mode register (output mode)
206pub mod ccmr1_output;
207/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
208
209You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CCMR1_Input)
212
213For information about available fields see [`mod@ccmr1_input`]
214module*/
215#[doc(alias = "CCMR1_Input")]
216pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
217///capture/compare mode register 1 (input mode)
218pub mod ccmr1_input;
219/**CCER (rw) register accessor: capture/compare enable register
220
221You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CCER)
224
225For information about available fields see [`mod@ccer`]
226module*/
227pub type CCER = crate::Reg<ccer::CCERrs>;
228///capture/compare enable register
229pub mod ccer;
230/**CNT (rw) register accessor: counter
231
232You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CNT)
235
236For information about available fields see [`mod@cnt`]
237module*/
238pub type CNT = crate::Reg<cnt::CNTrs>;
239///counter
240pub mod cnt;
241/**PSC (rw) register accessor: prescaler
242
243You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
244
245See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:PSC)
246
247For information about available fields see [`mod@psc`]
248module*/
249pub type PSC = crate::Reg<psc::PSCrs>;
250///prescaler
251pub mod psc;
252/**ARR (rw) register accessor: auto-reload register
253
254You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
255
256See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:ARR)
257
258For information about available fields see [`mod@arr`]
259module*/
260pub type ARR = crate::Reg<arr::ARRrs>;
261///auto-reload register
262pub mod arr;
263/**RCR (rw) register accessor: repetition counter register
264
265You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
266
267See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:RCR)
268
269For information about available fields see [`mod@rcr`]
270module*/
271pub type RCR = crate::Reg<rcr::RCRrs>;
272///repetition counter register
273pub mod rcr;
274/**CCR (rw) register accessor: capture/compare register
275
276You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
277
278See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:CCR[1])
279
280For information about available fields see [`mod@ccr`]
281module*/
282pub type CCR = crate::Reg<ccr::CCRrs>;
283///capture/compare register
284pub mod ccr;
285/**BDTR (rw) register accessor: break and dead-time register
286
287You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
288
289See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:BDTR)
290
291For information about available fields see [`mod@bdtr`]
292module*/
293pub type BDTR = crate::Reg<bdtr::BDTRrs>;
294///break and dead-time register
295pub mod bdtr;
296/**DCR (rw) register accessor: DMA control register
297
298You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
299
300See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:DCR)
301
302For information about available fields see [`mod@dcr`]
303module*/
304pub type DCR = crate::Reg<dcr::DCRrs>;
305///DMA control register
306pub mod dcr;
307/**DMAR (rw) register accessor: DMA address for full transfer
308
309You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
310
311See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15:DMAR)
312
313For information about available fields see [`mod@dmar`]
314module*/
315pub type DMAR = crate::Reg<dmar::DMARrs>;
316///DMA address for full transfer
317pub mod dmar;
stm32f3_staging/stm32f302/tim15.rs

stm32f3_staging/stm32f302/
tim15.rs
