stm32f3_staging/stm32f302/
tim1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 4],
19    bdtr: BDTR,
20    dcr: DCR,
21    dmar: DMAR,
22    _reserved17: [u8; 0x04],
23    ccmr3_output: CCMR3_OUTPUT,
24    ccr5: CCR5,
25    ccr6: CCR6,
26    or: OR,
27}
28impl RegisterBlock {
29    ///0x00 - control register 1
30    #[inline(always)]
31    pub const fn cr1(&self) -> &CR1 {
32        &self.cr1
33    }
34    ///0x04 - control register 2
35    #[inline(always)]
36    pub const fn cr2(&self) -> &CR2 {
37        &self.cr2
38    }
39    ///0x08 - slave mode control register
40    #[inline(always)]
41    pub const fn smcr(&self) -> &SMCR {
42        &self.smcr
43    }
44    ///0x0c - DMA/Interrupt enable register
45    #[inline(always)]
46    pub const fn dier(&self) -> &DIER {
47        &self.dier
48    }
49    ///0x10 - status register
50    #[inline(always)]
51    pub const fn sr(&self) -> &SR {
52        &self.sr
53    }
54    ///0x14 - event generation register
55    #[inline(always)]
56    pub const fn egr(&self) -> &EGR {
57        &self.egr
58    }
59    ///0x18 - capture/compare mode register 1 (input mode)
60    #[inline(always)]
61    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x18 - capture/compare mode register (output mode)
65    #[inline(always)]
66    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
67        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
68    }
69    ///0x1c - capture/compare mode register 2 (input mode)
70    #[inline(always)]
71    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
72        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
73    }
74    ///0x1c - capture/compare mode register (output mode)
75    #[inline(always)]
76    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
77        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
78    }
79    ///0x20 - capture/compare enable register
80    #[inline(always)]
81    pub const fn ccer(&self) -> &CCER {
82        &self.ccer
83    }
84    ///0x24 - counter
85    #[inline(always)]
86    pub const fn cnt(&self) -> &CNT {
87        &self.cnt
88    }
89    ///0x28 - prescaler
90    #[inline(always)]
91    pub const fn psc(&self) -> &PSC {
92        &self.psc
93    }
94    ///0x2c - auto-reload register
95    #[inline(always)]
96    pub const fn arr(&self) -> &ARR {
97        &self.arr
98    }
99    ///0x30 - repetition counter register
100    #[inline(always)]
101    pub const fn rcr(&self) -> &RCR {
102        &self.rcr
103    }
104    ///0x34..0x44 - capture/compare register
105    ///
106    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
107    #[inline(always)]
108    pub const fn ccr(&self, n: usize) -> &CCR {
109        &self.ccr[n]
110    }
111    ///Iterator for array of:
112    ///0x34..0x44 - capture/compare register
113    #[inline(always)]
114    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
115        self.ccr.iter()
116    }
117    ///0x34 - capture/compare register
118    #[inline(always)]
119    pub const fn ccr1(&self) -> &CCR {
120        self.ccr(0)
121    }
122    ///0x38 - capture/compare register
123    #[inline(always)]
124    pub const fn ccr2(&self) -> &CCR {
125        self.ccr(1)
126    }
127    ///0x3c - capture/compare register
128    #[inline(always)]
129    pub const fn ccr3(&self) -> &CCR {
130        self.ccr(2)
131    }
132    ///0x40 - capture/compare register
133    #[inline(always)]
134    pub const fn ccr4(&self) -> &CCR {
135        self.ccr(3)
136    }
137    ///0x44 - break and dead-time register
138    #[inline(always)]
139    pub const fn bdtr(&self) -> &BDTR {
140        &self.bdtr
141    }
142    ///0x48 - DMA control register
143    #[inline(always)]
144    pub const fn dcr(&self) -> &DCR {
145        &self.dcr
146    }
147    ///0x4c - DMA address for full transfer
148    #[inline(always)]
149    pub const fn dmar(&self) -> &DMAR {
150        &self.dmar
151    }
152    ///0x54 - capture/compare mode register 3 (output mode)
153    #[inline(always)]
154    pub const fn ccmr3_output(&self) -> &CCMR3_OUTPUT {
155        &self.ccmr3_output
156    }
157    ///0x58 - capture/compare register
158    #[inline(always)]
159    pub const fn ccr5(&self) -> &CCR5 {
160        &self.ccr5
161    }
162    ///0x5c - capture/compare register
163    #[inline(always)]
164    pub const fn ccr6(&self) -> &CCR6 {
165        &self.ccr6
166    }
167    ///0x60 - option registers
168    #[inline(always)]
169    pub const fn or(&self) -> &OR {
170        &self.or
171    }
172}
173/**CR1 (rw) register accessor: control register 1
174
175You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
176
177See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CR1)
178
179For information about available fields see [`mod@cr1`]
180module*/
181pub type CR1 = crate::Reg<cr1::CR1rs>;
182///control register 1
183pub mod cr1;
184/**CR2 (rw) register accessor: control register 2
185
186You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
187
188See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CR2)
189
190For information about available fields see [`mod@cr2`]
191module*/
192pub type CR2 = crate::Reg<cr2::CR2rs>;
193///control register 2
194pub mod cr2;
195/**SMCR (rw) register accessor: slave mode control register
196
197You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
198
199See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:SMCR)
200
201For information about available fields see [`mod@smcr`]
202module*/
203pub type SMCR = crate::Reg<smcr::SMCRrs>;
204///slave mode control register
205pub mod smcr;
206/**DIER (rw) register accessor: DMA/Interrupt enable register
207
208You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
209
210See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:DIER)
211
212For information about available fields see [`mod@dier`]
213module*/
214pub type DIER = crate::Reg<dier::DIERrs>;
215///DMA/Interrupt enable register
216pub mod dier;
217/**SR (rw) register accessor: status register
218
219You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
220
221See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:SR)
222
223For information about available fields see [`mod@sr`]
224module*/
225pub type SR = crate::Reg<sr::SRrs>;
226///status register
227pub mod sr;
228/**EGR (w) register accessor: event generation register
229
230You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
231
232See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:EGR)
233
234For information about available fields see [`mod@egr`]
235module*/
236pub type EGR = crate::Reg<egr::EGRrs>;
237///event generation register
238pub mod egr;
239/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
240
241You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
242
243See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCMR1_Output)
244
245For information about available fields see [`mod@ccmr1_output`]
246module*/
247#[doc(alias = "CCMR1_Output")]
248pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
249///capture/compare mode register (output mode)
250pub mod ccmr1_output;
251/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
252
253You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
254
255See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCMR1_Input)
256
257For information about available fields see [`mod@ccmr1_input`]
258module*/
259#[doc(alias = "CCMR1_Input")]
260pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
261///capture/compare mode register 1 (input mode)
262pub mod ccmr1_input;
263/**CCMR2_Output (rw) register accessor: capture/compare mode register (output mode)
264
265You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
266
267See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCMR2_Output)
268
269For information about available fields see [`mod@ccmr2_output`]
270module*/
271#[doc(alias = "CCMR2_Output")]
272pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
273///capture/compare mode register (output mode)
274pub mod ccmr2_output;
275/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
276
277You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
278
279See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCMR2_Input)
280
281For information about available fields see [`mod@ccmr2_input`]
282module*/
283#[doc(alias = "CCMR2_Input")]
284pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
285///capture/compare mode register 2 (input mode)
286pub mod ccmr2_input;
287/**CCER (rw) register accessor: capture/compare enable register
288
289You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
290
291See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCER)
292
293For information about available fields see [`mod@ccer`]
294module*/
295pub type CCER = crate::Reg<ccer::CCERrs>;
296///capture/compare enable register
297pub mod ccer;
298/**CNT (rw) register accessor: counter
299
300You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
301
302See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CNT)
303
304For information about available fields see [`mod@cnt`]
305module*/
306pub type CNT = crate::Reg<cnt::CNTrs>;
307///counter
308pub mod cnt;
309/**PSC (rw) register accessor: prescaler
310
311You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
312
313See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:PSC)
314
315For information about available fields see [`mod@psc`]
316module*/
317pub type PSC = crate::Reg<psc::PSCrs>;
318///prescaler
319pub mod psc;
320/**ARR (rw) register accessor: auto-reload register
321
322You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
323
324See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:ARR)
325
326For information about available fields see [`mod@arr`]
327module*/
328pub type ARR = crate::Reg<arr::ARRrs>;
329///auto-reload register
330pub mod arr;
331/**RCR (rw) register accessor: repetition counter register
332
333You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
334
335See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:RCR)
336
337For information about available fields see [`mod@rcr`]
338module*/
339pub type RCR = crate::Reg<rcr::RCRrs>;
340///repetition counter register
341pub mod rcr;
342/**CCR (rw) register accessor: capture/compare register
343
344You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
345
346See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCR[1])
347
348For information about available fields see [`mod@ccr`]
349module*/
350pub type CCR = crate::Reg<ccr::CCRrs>;
351///capture/compare register
352pub mod ccr;
353/**BDTR (rw) register accessor: break and dead-time register
354
355You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
356
357See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:BDTR)
358
359For information about available fields see [`mod@bdtr`]
360module*/
361pub type BDTR = crate::Reg<bdtr::BDTRrs>;
362///break and dead-time register
363pub mod bdtr;
364/**DCR (rw) register accessor: DMA control register
365
366You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
367
368See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:DCR)
369
370For information about available fields see [`mod@dcr`]
371module*/
372pub type DCR = crate::Reg<dcr::DCRrs>;
373///DMA control register
374pub mod dcr;
375/**DMAR (rw) register accessor: DMA address for full transfer
376
377You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
378
379See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:DMAR)
380
381For information about available fields see [`mod@dmar`]
382module*/
383pub type DMAR = crate::Reg<dmar::DMARrs>;
384///DMA address for full transfer
385pub mod dmar;
386/**CCMR3_Output (rw) register accessor: capture/compare mode register 3 (output mode)
387
388You can [`read`](crate::Reg::read) this register and get [`ccmr3_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr3_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
389
390See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCMR3_Output)
391
392For information about available fields see [`mod@ccmr3_output`]
393module*/
394#[doc(alias = "CCMR3_Output")]
395pub type CCMR3_OUTPUT = crate::Reg<ccmr3_output::CCMR3_OUTPUTrs>;
396///capture/compare mode register 3 (output mode)
397pub mod ccmr3_output;
398/**CCR5 (rw) register accessor: capture/compare register
399
400You can [`read`](crate::Reg::read) this register and get [`ccr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
401
402See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:CCR5)
403
404For information about available fields see [`mod@ccr5`]
405module*/
406pub type CCR5 = crate::Reg<ccr5::CCR5rs>;
407///capture/compare register
408pub mod ccr5;
409pub use ccr as ccr6;
410pub use CCR as CCR6;
411/**OR (rw) register accessor: option registers
412
413You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
414
415See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1:OR)
416
417For information about available fields see [`mod@or`]
418module*/
419pub type OR = crate::Reg<or::ORrs>;
420///option registers
421pub mod or;
stm32f3_staging/stm32f302/tim1.rs

stm32f3_staging/stm32f302/
tim1.rs
