stm32f3_staging/stm32f302/crc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**reset bit
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RESETW {
11    ///1: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
12    Reset = 1,
13}
14impl From<RESETW> for bool {
15    #[inline(always)]
16    fn from(variant: RESETW) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `RESET` reader - reset bit
21pub type RESET_R = crate::BitReader<RESETW>;
22impl RESET_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<RESETW> {
26        match self.bits {
27            true => Some(RESETW::Reset),
28            _ => None,
29        }
30    }
31    ///Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == RESETW::Reset
35    }
36}
37///Field `RESET` writer - reset bit
38pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG, RESETW>;
39impl<'a, REG> RESET_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(RESETW::Reset)
47    }
48}
49/**Polynomial size
50
51Value on reset: 0*/
52#[cfg_attr(feature = "defmt", derive(defmt::Format))]
53#[derive(Clone, Copy, Debug, PartialEq, Eq)]
54#[repr(u8)]
55pub enum POLYSIZE {
56    ///0: 32-bit polynomial
57    Polysize32 = 0,
58    ///1: 16-bit polynomial
59    Polysize16 = 1,
60    ///2: 8-bit polynomial
61    Polysize8 = 2,
62    ///3: 7-bit polynomial
63    Polysize7 = 3,
64}
65impl From<POLYSIZE> for u8 {
66    #[inline(always)]
67    fn from(variant: POLYSIZE) -> Self {
68        variant as _
69    }
70}
71impl crate::FieldSpec for POLYSIZE {
72    type Ux = u8;
73}
74impl crate::IsEnum for POLYSIZE {}
75///Field `POLYSIZE` reader - Polynomial size
76pub type POLYSIZE_R = crate::FieldReader<POLYSIZE>;
77impl POLYSIZE_R {
78    ///Get enumerated values variant
79    #[inline(always)]
80    pub const fn variant(&self) -> POLYSIZE {
81        match self.bits {
82            0 => POLYSIZE::Polysize32,
83            1 => POLYSIZE::Polysize16,
84            2 => POLYSIZE::Polysize8,
85            3 => POLYSIZE::Polysize7,
86            _ => unreachable!(),
87        }
88    }
89    ///32-bit polynomial
90    #[inline(always)]
91    pub fn is_polysize32(&self) -> bool {
92        *self == POLYSIZE::Polysize32
93    }
94    ///16-bit polynomial
95    #[inline(always)]
96    pub fn is_polysize16(&self) -> bool {
97        *self == POLYSIZE::Polysize16
98    }
99    ///8-bit polynomial
100    #[inline(always)]
101    pub fn is_polysize8(&self) -> bool {
102        *self == POLYSIZE::Polysize8
103    }
104    ///7-bit polynomial
105    #[inline(always)]
106    pub fn is_polysize7(&self) -> bool {
107        *self == POLYSIZE::Polysize7
108    }
109}
110///Field `POLYSIZE` writer - Polynomial size
111pub type POLYSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, POLYSIZE, crate::Safe>;
112impl<'a, REG> POLYSIZE_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115    REG::Ux: From<u8>,
116{
117    ///32-bit polynomial
118    #[inline(always)]
119    pub fn polysize32(self) -> &'a mut crate::W<REG> {
120        self.variant(POLYSIZE::Polysize32)
121    }
122    ///16-bit polynomial
123    #[inline(always)]
124    pub fn polysize16(self) -> &'a mut crate::W<REG> {
125        self.variant(POLYSIZE::Polysize16)
126    }
127    ///8-bit polynomial
128    #[inline(always)]
129    pub fn polysize8(self) -> &'a mut crate::W<REG> {
130        self.variant(POLYSIZE::Polysize8)
131    }
132    ///7-bit polynomial
133    #[inline(always)]
134    pub fn polysize7(self) -> &'a mut crate::W<REG> {
135        self.variant(POLYSIZE::Polysize7)
136    }
137}
138/**Reverse input data
139
140Value on reset: 0*/
141#[cfg_attr(feature = "defmt", derive(defmt::Format))]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143#[repr(u8)]
144pub enum REV_IN {
145    ///0: Bit order not affected
146    Normal = 0,
147    ///1: Bit reversal done by byte
148    Byte = 1,
149    ///2: Bit reversal done by half-word
150    HalfWord = 2,
151    ///3: Bit reversal done by word
152    Word = 3,
153}
154impl From<REV_IN> for u8 {
155    #[inline(always)]
156    fn from(variant: REV_IN) -> Self {
157        variant as _
158    }
159}
160impl crate::FieldSpec for REV_IN {
161    type Ux = u8;
162}
163impl crate::IsEnum for REV_IN {}
164///Field `REV_IN` reader - Reverse input data
165pub type REV_IN_R = crate::FieldReader<REV_IN>;
166impl REV_IN_R {
167    ///Get enumerated values variant
168    #[inline(always)]
169    pub const fn variant(&self) -> REV_IN {
170        match self.bits {
171            0 => REV_IN::Normal,
172            1 => REV_IN::Byte,
173            2 => REV_IN::HalfWord,
174            3 => REV_IN::Word,
175            _ => unreachable!(),
176        }
177    }
178    ///Bit order not affected
179    #[inline(always)]
180    pub fn is_normal(&self) -> bool {
181        *self == REV_IN::Normal
182    }
183    ///Bit reversal done by byte
184    #[inline(always)]
185    pub fn is_byte(&self) -> bool {
186        *self == REV_IN::Byte
187    }
188    ///Bit reversal done by half-word
189    #[inline(always)]
190    pub fn is_half_word(&self) -> bool {
191        *self == REV_IN::HalfWord
192    }
193    ///Bit reversal done by word
194    #[inline(always)]
195    pub fn is_word(&self) -> bool {
196        *self == REV_IN::Word
197    }
198}
199///Field `REV_IN` writer - Reverse input data
200pub type REV_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, REV_IN, crate::Safe>;
201impl<'a, REG> REV_IN_W<'a, REG>
202where
203    REG: crate::Writable + crate::RegisterSpec,
204    REG::Ux: From<u8>,
205{
206    ///Bit order not affected
207    #[inline(always)]
208    pub fn normal(self) -> &'a mut crate::W<REG> {
209        self.variant(REV_IN::Normal)
210    }
211    ///Bit reversal done by byte
212    #[inline(always)]
213    pub fn byte(self) -> &'a mut crate::W<REG> {
214        self.variant(REV_IN::Byte)
215    }
216    ///Bit reversal done by half-word
217    #[inline(always)]
218    pub fn half_word(self) -> &'a mut crate::W<REG> {
219        self.variant(REV_IN::HalfWord)
220    }
221    ///Bit reversal done by word
222    #[inline(always)]
223    pub fn word(self) -> &'a mut crate::W<REG> {
224        self.variant(REV_IN::Word)
225    }
226}
227/**Reverse output data
228
229Value on reset: 0*/
230#[cfg_attr(feature = "defmt", derive(defmt::Format))]
231#[derive(Clone, Copy, Debug, PartialEq, Eq)]
232pub enum REV_OUT {
233    ///0: Bit order not affected
234    Normal = 0,
235    ///1: Bit reversed output
236    Reversed = 1,
237}
238impl From<REV_OUT> for bool {
239    #[inline(always)]
240    fn from(variant: REV_OUT) -> Self {
241        variant as u8 != 0
242    }
243}
244///Field `REV_OUT` reader - Reverse output data
245pub type REV_OUT_R = crate::BitReader<REV_OUT>;
246impl REV_OUT_R {
247    ///Get enumerated values variant
248    #[inline(always)]
249    pub const fn variant(&self) -> REV_OUT {
250        match self.bits {
251            false => REV_OUT::Normal,
252            true => REV_OUT::Reversed,
253        }
254    }
255    ///Bit order not affected
256    #[inline(always)]
257    pub fn is_normal(&self) -> bool {
258        *self == REV_OUT::Normal
259    }
260    ///Bit reversed output
261    #[inline(always)]
262    pub fn is_reversed(&self) -> bool {
263        *self == REV_OUT::Reversed
264    }
265}
266///Field `REV_OUT` writer - Reverse output data
267pub type REV_OUT_W<'a, REG> = crate::BitWriter<'a, REG, REV_OUT>;
268impl<'a, REG> REV_OUT_W<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271{
272    ///Bit order not affected
273    #[inline(always)]
274    pub fn normal(self) -> &'a mut crate::W<REG> {
275        self.variant(REV_OUT::Normal)
276    }
277    ///Bit reversed output
278    #[inline(always)]
279    pub fn reversed(self) -> &'a mut crate::W<REG> {
280        self.variant(REV_OUT::Reversed)
281    }
282}
283impl R {
284    ///Bit 0 - reset bit
285    #[inline(always)]
286    pub fn reset(&self) -> RESET_R {
287        RESET_R::new((self.bits & 1) != 0)
288    }
289    ///Bits 3:4 - Polynomial size
290    #[inline(always)]
291    pub fn polysize(&self) -> POLYSIZE_R {
292        POLYSIZE_R::new(((self.bits >> 3) & 3) as u8)
293    }
294    ///Bits 5:6 - Reverse input data
295    #[inline(always)]
296    pub fn rev_in(&self) -> REV_IN_R {
297        REV_IN_R::new(((self.bits >> 5) & 3) as u8)
298    }
299    ///Bit 7 - Reverse output data
300    #[inline(always)]
301    pub fn rev_out(&self) -> REV_OUT_R {
302        REV_OUT_R::new(((self.bits >> 7) & 1) != 0)
303    }
304}
305impl core::fmt::Debug for R {
306    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
307        f.debug_struct("CR")
308            .field("reset", &self.reset())
309            .field("polysize", &self.polysize())
310            .field("rev_in", &self.rev_in())
311            .field("rev_out", &self.rev_out())
312            .finish()
313    }
314}
315impl W {
316    ///Bit 0 - reset bit
317    #[inline(always)]
318    pub fn reset(&mut self) -> RESET_W<CRrs> {
319        RESET_W::new(self, 0)
320    }
321    ///Bits 3:4 - Polynomial size
322    #[inline(always)]
323    pub fn polysize(&mut self) -> POLYSIZE_W<CRrs> {
324        POLYSIZE_W::new(self, 3)
325    }
326    ///Bits 5:6 - Reverse input data
327    #[inline(always)]
328    pub fn rev_in(&mut self) -> REV_IN_W<CRrs> {
329        REV_IN_W::new(self, 5)
330    }
331    ///Bit 7 - Reverse output data
332    #[inline(always)]
333    pub fn rev_out(&mut self) -> REV_OUT_W<CRrs> {
334        REV_OUT_W::new(self, 7)
335    }
336}
337/**Control register
338
339You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#CRC:CR)*/
342pub struct CRrs;
343impl crate::RegisterSpec for CRrs {
344    type Ux = u32;
345}
346///`read()` method returns [`cr::R`](R) reader structure
347impl crate::Readable for CRrs {}
348///`write(|w| ..)` method takes [`cr::W`](W) writer structure
349impl crate::Writable for CRrs {
350    type Safety = crate::Unsafe;
351    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
352    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
353}
354///`reset()` method sets CR to value 0
355impl crate::Resettable for CRrs {
356    const RESET_VALUE: u32 = 0;
357}
stm32f3_staging/stm32f302/crc/cr.rs

stm32f3_staging/stm32f302/crc/
cr.rs
