stm32f3_copterust/stm32f373/
dac2.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - control register"]
5    pub cr: CR,
6    #[doc = "0x04 - software trigger register"]
7    pub swtrigr: SWTRIGR,
8    #[doc = "0x08 - channel1 12-bit right-aligned data holding register"]
9    pub dhr12r1: DHR12R1,
10    #[doc = "0x0c - DAC channel1 12-bit left aligned data holding register"]
11    pub dhr12l1: DHR12L1,
12    #[doc = "0x10 - DAC channel1 8-bit right aligned data holding register"]
13    pub dhr8r1: DHR8R1,
14    _reserved5: [u8; 24usize],
15    #[doc = "0x2c - DAC channel1 data output register"]
16    pub dor1: DOR1,
17    _reserved6: [u8; 4usize],
18    #[doc = "0x34 - DAC status register"]
19    pub sr: SR,
20}
21#[doc = "control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](cr) module"]
22pub type CR = crate::Reg<u32, _CR>;
23#[allow(missing_docs)]
24#[doc(hidden)]
25pub struct _CR;
26#[doc = "`read()` method returns [cr::R](cr::R) reader structure"]
27impl crate::Readable for CR {}
28#[doc = "`write(|w| ..)` method takes [cr::W](cr::W) writer structure"]
29impl crate::Writable for CR {}
30#[doc = "control register"]
31pub mod cr;
32#[doc = "software trigger register\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigr](swtrigr) module"]
33pub type SWTRIGR = crate::Reg<u32, _SWTRIGR>;
34#[allow(missing_docs)]
35#[doc(hidden)]
36pub struct _SWTRIGR;
37#[doc = "`write(|w| ..)` method takes [swtrigr::W](swtrigr::W) writer structure"]
38impl crate::Writable for SWTRIGR {}
39#[doc = "software trigger register"]
40pub mod swtrigr;
41#[doc = "channel1 12-bit right-aligned data holding register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12r1](dhr12r1) module"]
42pub type DHR12R1 = crate::Reg<u32, _DHR12R1>;
43#[allow(missing_docs)]
44#[doc(hidden)]
45pub struct _DHR12R1;
46#[doc = "`read()` method returns [dhr12r1::R](dhr12r1::R) reader structure"]
47impl crate::Readable for DHR12R1 {}
48#[doc = "`write(|w| ..)` method takes [dhr12r1::W](dhr12r1::W) writer structure"]
49impl crate::Writable for DHR12R1 {}
50#[doc = "channel1 12-bit right-aligned data holding register"]
51pub mod dhr12r1;
52#[doc = "DAC channel1 12-bit left aligned data holding register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12l1](dhr12l1) module"]
53pub type DHR12L1 = crate::Reg<u32, _DHR12L1>;
54#[allow(missing_docs)]
55#[doc(hidden)]
56pub struct _DHR12L1;
57#[doc = "`read()` method returns [dhr12l1::R](dhr12l1::R) reader structure"]
58impl crate::Readable for DHR12L1 {}
59#[doc = "`write(|w| ..)` method takes [dhr12l1::W](dhr12l1::W) writer structure"]
60impl crate::Writable for DHR12L1 {}
61#[doc = "DAC channel1 12-bit left aligned data holding register"]
62pub mod dhr12l1;
63#[doc = "DAC channel1 8-bit right aligned data holding register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr8r1](dhr8r1) module"]
64pub type DHR8R1 = crate::Reg<u32, _DHR8R1>;
65#[allow(missing_docs)]
66#[doc(hidden)]
67pub struct _DHR8R1;
68#[doc = "`read()` method returns [dhr8r1::R](dhr8r1::R) reader structure"]
69impl crate::Readable for DHR8R1 {}
70#[doc = "`write(|w| ..)` method takes [dhr8r1::W](dhr8r1::W) writer structure"]
71impl crate::Writable for DHR8R1 {}
72#[doc = "DAC channel1 8-bit right aligned data holding register"]
73pub mod dhr8r1;
74#[doc = "DAC channel1 data output register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dor1](dor1) module"]
75pub type DOR1 = crate::Reg<u32, _DOR1>;
76#[allow(missing_docs)]
77#[doc(hidden)]
78pub struct _DOR1;
79#[doc = "`read()` method returns [dor1::R](dor1::R) reader structure"]
80impl crate::Readable for DOR1 {}
81#[doc = "DAC channel1 data output register"]
82pub mod dor1;
83#[doc = "DAC status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](sr) module"]
84pub type SR = crate::Reg<u32, _SR>;
85#[allow(missing_docs)]
86#[doc(hidden)]
87pub struct _SR;
88#[doc = "`read()` method returns [sr::R](sr::R) reader structure"]
89impl crate::Readable for SR {}
90#[doc = "`write(|w| ..)` method takes [sr::W](sr::W) writer structure"]
91impl crate::Writable for SR {}
92#[doc = "DAC status register"]
93pub mod sr;
stm32f3_copterust/stm32f373/dac2.rs

stm32f3_copterust/stm32f373/
dac2.rs
