stm32f2/stm32f215/dbgmcu/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `DBG_SLEEP` reader - DBG_SLEEP
6pub type DBG_SLEEP_R = crate::BitReader;
7///Field `DBG_SLEEP` writer - DBG_SLEEP
8pub type DBG_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DBG_STOP` reader - DBG_STOP
10pub type DBG_STOP_R = crate::BitReader;
11///Field `DBG_STOP` writer - DBG_STOP
12pub type DBG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DBG_STANDBY` reader - DBG_STANDBY
14pub type DBG_STANDBY_R = crate::BitReader;
15///Field `DBG_STANDBY` writer - DBG_STANDBY
16pub type DBG_STANDBY_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `TRACE_IOEN` reader - TRACE_IOEN
18pub type TRACE_IOEN_R = crate::BitReader;
19///Field `TRACE_IOEN` writer - TRACE_IOEN
20pub type TRACE_IOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TRACE_MODE` reader - TRACE_MODE
22pub type TRACE_MODE_R = crate::FieldReader;
23///Field `TRACE_MODE` writer - TRACE_MODE
24pub type TRACE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26    ///Bit 0 - DBG_SLEEP
27    #[inline(always)]
28    pub fn dbg_sleep(&self) -> DBG_SLEEP_R {
29        DBG_SLEEP_R::new((self.bits & 1) != 0)
30    }
31    ///Bit 1 - DBG_STOP
32    #[inline(always)]
33    pub fn dbg_stop(&self) -> DBG_STOP_R {
34        DBG_STOP_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    ///Bit 2 - DBG_STANDBY
37    #[inline(always)]
38    pub fn dbg_standby(&self) -> DBG_STANDBY_R {
39        DBG_STANDBY_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    ///Bit 5 - TRACE_IOEN
42    #[inline(always)]
43    pub fn trace_ioen(&self) -> TRACE_IOEN_R {
44        TRACE_IOEN_R::new(((self.bits >> 5) & 1) != 0)
45    }
46    ///Bits 6:7 - TRACE_MODE
47    #[inline(always)]
48    pub fn trace_mode(&self) -> TRACE_MODE_R {
49        TRACE_MODE_R::new(((self.bits >> 6) & 3) as u8)
50    }
51}
52impl core::fmt::Debug for R {
53    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
54        f.debug_struct("CR")
55            .field("dbg_sleep", &self.dbg_sleep())
56            .field("dbg_stop", &self.dbg_stop())
57            .field("dbg_standby", &self.dbg_standby())
58            .field("trace_ioen", &self.trace_ioen())
59            .field("trace_mode", &self.trace_mode())
60            .finish()
61    }
62}
63impl W {
64    ///Bit 0 - DBG_SLEEP
65    #[inline(always)]
66    pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<CRrs> {
67        DBG_SLEEP_W::new(self, 0)
68    }
69    ///Bit 1 - DBG_STOP
70    #[inline(always)]
71    pub fn dbg_stop(&mut self) -> DBG_STOP_W<CRrs> {
72        DBG_STOP_W::new(self, 1)
73    }
74    ///Bit 2 - DBG_STANDBY
75    #[inline(always)]
76    pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<CRrs> {
77        DBG_STANDBY_W::new(self, 2)
78    }
79    ///Bit 5 - TRACE_IOEN
80    #[inline(always)]
81    pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<CRrs> {
82        TRACE_IOEN_W::new(self, 5)
83    }
84    ///Bits 6:7 - TRACE_MODE
85    #[inline(always)]
86    pub fn trace_mode(&mut self) -> TRACE_MODE_W<CRrs> {
87        TRACE_MODE_W::new(self, 6)
88    }
89}
90/**Control Register
91
92You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#DBGMCU:CR)*/
95pub struct CRrs;
96impl crate::RegisterSpec for CRrs {
97    type Ux = u32;
98}
99///`read()` method returns [`cr::R`](R) reader structure
100impl crate::Readable for CRrs {}
101///`write(|w| ..)` method takes [`cr::W`](W) writer structure
102impl crate::Writable for CRrs {
103    type Safety = crate::Unsafe;
104}
105///`reset()` method sets CR to value 0
106impl crate::Resettable for CRrs {}
stm32f2/stm32f215/dbgmcu/cr.rs

stm32f2/stm32f215/dbgmcu/
cr.rs
