stm32f2/stm32f215/sdio/
sta.rs1#[doc = "Register `STA` reader"]
2pub struct R(crate::R<STA_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<STA_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<STA_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<STA_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `CEATAEND` reader - CE-ATA command completion signal received for CMD61"]
17pub type CEATAEND_R = crate::BitReader<bool>;
18#[doc = "Field `SDIOIT` reader - SDIO interrupt received"]
19pub type SDIOIT_R = crate::BitReader<bool>;
20#[doc = "Field `RXDAVL` reader - Data available in receive FIFO"]
21pub type RXDAVL_R = crate::BitReader<bool>;
22#[doc = "Field `TXDAVL` reader - Data available in transmit FIFO"]
23pub type TXDAVL_R = crate::BitReader<bool>;
24#[doc = "Field `RXFIFOE` reader - Receive FIFO empty"]
25pub type RXFIFOE_R = crate::BitReader<bool>;
26#[doc = "Field `TXFIFOE` reader - Transmit FIFO empty"]
27pub type TXFIFOE_R = crate::BitReader<bool>;
28#[doc = "Field `RXFIFOF` reader - Receive FIFO full"]
29pub type RXFIFOF_R = crate::BitReader<bool>;
30#[doc = "Field `TXFIFOF` reader - Transmit FIFO full"]
31pub type TXFIFOF_R = crate::BitReader<bool>;
32#[doc = "Field `RXFIFOHF` reader - Receive FIFO half full: there are at least 8 words in the FIFO"]
33pub type RXFIFOHF_R = crate::BitReader<bool>;
34#[doc = "Field `TXFIFOHE` reader - Transmit FIFO half empty: at least 8 words can be written into the FIFO"]
35pub type TXFIFOHE_R = crate::BitReader<bool>;
36#[doc = "Field `RXACT` reader - Data receive in progress"]
37pub type RXACT_R = crate::BitReader<bool>;
38#[doc = "Field `TXACT` reader - Data transmit in progress"]
39pub type TXACT_R = crate::BitReader<bool>;
40#[doc = "Field `CMDACT` reader - Command transfer in progress"]
41pub type CMDACT_R = crate::BitReader<bool>;
42#[doc = "Field `DBCKEND` reader - Data block sent/received (CRC check passed)"]
43pub type DBCKEND_R = crate::BitReader<bool>;
44#[doc = "Field `STBITERR` reader - Start bit not detected on all data signals in wide bus mode"]
45pub type STBITERR_R = crate::BitReader<bool>;
46#[doc = "Field `DATAEND` reader - Data end (data counter, SDIDCOUNT, is zero)"]
47pub type DATAEND_R = crate::BitReader<bool>;
48#[doc = "Field `CMDSENT` reader - Command sent (no response required)"]
49pub type CMDSENT_R = crate::BitReader<bool>;
50#[doc = "Field `CMDREND` reader - Command response received (CRC check passed)"]
51pub type CMDREND_R = crate::BitReader<bool>;
52#[doc = "Field `RXOVERR` reader - Received FIFO overrun error"]
53pub type RXOVERR_R = crate::BitReader<bool>;
54#[doc = "Field `TXUNDERR` reader - Transmit FIFO underrun error"]
55pub type TXUNDERR_R = crate::BitReader<bool>;
56#[doc = "Field `DTIMEOUT` reader - Data timeout"]
57pub type DTIMEOUT_R = crate::BitReader<bool>;
58#[doc = "Field `CTIMEOUT` reader - Command response timeout"]
59pub type CTIMEOUT_R = crate::BitReader<bool>;
60#[doc = "Field `DCRCFAIL` reader - Data block sent/received (CRC check failed)"]
61pub type DCRCFAIL_R = crate::BitReader<bool>;
62#[doc = "Field `CCRCFAIL` reader - Command response received (CRC check failed)"]
63pub type CCRCFAIL_R = crate::BitReader<bool>;
64impl R {
65 #[doc = "Bit 23 - CE-ATA command completion signal received for CMD61"]
66 #[inline(always)]
67 pub fn ceataend(&self) -> CEATAEND_R {
68 CEATAEND_R::new(((self.bits >> 23) & 1) != 0)
69 }
70 #[doc = "Bit 22 - SDIO interrupt received"]
71 #[inline(always)]
72 pub fn sdioit(&self) -> SDIOIT_R {
73 SDIOIT_R::new(((self.bits >> 22) & 1) != 0)
74 }
75 #[doc = "Bit 21 - Data available in receive FIFO"]
76 #[inline(always)]
77 pub fn rxdavl(&self) -> RXDAVL_R {
78 RXDAVL_R::new(((self.bits >> 21) & 1) != 0)
79 }
80 #[doc = "Bit 20 - Data available in transmit FIFO"]
81 #[inline(always)]
82 pub fn txdavl(&self) -> TXDAVL_R {
83 TXDAVL_R::new(((self.bits >> 20) & 1) != 0)
84 }
85 #[doc = "Bit 19 - Receive FIFO empty"]
86 #[inline(always)]
87 pub fn rxfifoe(&self) -> RXFIFOE_R {
88 RXFIFOE_R::new(((self.bits >> 19) & 1) != 0)
89 }
90 #[doc = "Bit 18 - Transmit FIFO empty"]
91 #[inline(always)]
92 pub fn txfifoe(&self) -> TXFIFOE_R {
93 TXFIFOE_R::new(((self.bits >> 18) & 1) != 0)
94 }
95 #[doc = "Bit 17 - Receive FIFO full"]
96 #[inline(always)]
97 pub fn rxfifof(&self) -> RXFIFOF_R {
98 RXFIFOF_R::new(((self.bits >> 17) & 1) != 0)
99 }
100 #[doc = "Bit 16 - Transmit FIFO full"]
101 #[inline(always)]
102 pub fn txfifof(&self) -> TXFIFOF_R {
103 TXFIFOF_R::new(((self.bits >> 16) & 1) != 0)
104 }
105 #[doc = "Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO"]
106 #[inline(always)]
107 pub fn rxfifohf(&self) -> RXFIFOHF_R {
108 RXFIFOHF_R::new(((self.bits >> 15) & 1) != 0)
109 }
110 #[doc = "Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO"]
111 #[inline(always)]
112 pub fn txfifohe(&self) -> TXFIFOHE_R {
113 TXFIFOHE_R::new(((self.bits >> 14) & 1) != 0)
114 }
115 #[doc = "Bit 13 - Data receive in progress"]
116 #[inline(always)]
117 pub fn rxact(&self) -> RXACT_R {
118 RXACT_R::new(((self.bits >> 13) & 1) != 0)
119 }
120 #[doc = "Bit 12 - Data transmit in progress"]
121 #[inline(always)]
122 pub fn txact(&self) -> TXACT_R {
123 TXACT_R::new(((self.bits >> 12) & 1) != 0)
124 }
125 #[doc = "Bit 11 - Command transfer in progress"]
126 #[inline(always)]
127 pub fn cmdact(&self) -> CMDACT_R {
128 CMDACT_R::new(((self.bits >> 11) & 1) != 0)
129 }
130 #[doc = "Bit 10 - Data block sent/received (CRC check passed)"]
131 #[inline(always)]
132 pub fn dbckend(&self) -> DBCKEND_R {
133 DBCKEND_R::new(((self.bits >> 10) & 1) != 0)
134 }
135 #[doc = "Bit 9 - Start bit not detected on all data signals in wide bus mode"]
136 #[inline(always)]
137 pub fn stbiterr(&self) -> STBITERR_R {
138 STBITERR_R::new(((self.bits >> 9) & 1) != 0)
139 }
140 #[doc = "Bit 8 - Data end (data counter, SDIDCOUNT, is zero)"]
141 #[inline(always)]
142 pub fn dataend(&self) -> DATAEND_R {
143 DATAEND_R::new(((self.bits >> 8) & 1) != 0)
144 }
145 #[doc = "Bit 7 - Command sent (no response required)"]
146 #[inline(always)]
147 pub fn cmdsent(&self) -> CMDSENT_R {
148 CMDSENT_R::new(((self.bits >> 7) & 1) != 0)
149 }
150 #[doc = "Bit 6 - Command response received (CRC check passed)"]
151 #[inline(always)]
152 pub fn cmdrend(&self) -> CMDREND_R {
153 CMDREND_R::new(((self.bits >> 6) & 1) != 0)
154 }
155 #[doc = "Bit 5 - Received FIFO overrun error"]
156 #[inline(always)]
157 pub fn rxoverr(&self) -> RXOVERR_R {
158 RXOVERR_R::new(((self.bits >> 5) & 1) != 0)
159 }
160 #[doc = "Bit 4 - Transmit FIFO underrun error"]
161 #[inline(always)]
162 pub fn txunderr(&self) -> TXUNDERR_R {
163 TXUNDERR_R::new(((self.bits >> 4) & 1) != 0)
164 }
165 #[doc = "Bit 3 - Data timeout"]
166 #[inline(always)]
167 pub fn dtimeout(&self) -> DTIMEOUT_R {
168 DTIMEOUT_R::new(((self.bits >> 3) & 1) != 0)
169 }
170 #[doc = "Bit 2 - Command response timeout"]
171 #[inline(always)]
172 pub fn ctimeout(&self) -> CTIMEOUT_R {
173 CTIMEOUT_R::new(((self.bits >> 2) & 1) != 0)
174 }
175 #[doc = "Bit 1 - Data block sent/received (CRC check failed)"]
176 #[inline(always)]
177 pub fn dcrcfail(&self) -> DCRCFAIL_R {
178 DCRCFAIL_R::new(((self.bits >> 1) & 1) != 0)
179 }
180 #[doc = "Bit 0 - Command response received (CRC check failed)"]
181 #[inline(always)]
182 pub fn ccrcfail(&self) -> CCRCFAIL_R {
183 CCRCFAIL_R::new((self.bits & 1) != 0)
184 }
185}
186#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"]
187pub struct STA_SPEC;
188impl crate::RegisterSpec for STA_SPEC {
189 type Ux = u32;
190}
191#[doc = "`read()` method returns [sta::R](R) reader structure"]
192impl crate::Readable for STA_SPEC {
193 type Reader = R;
194}
195#[doc = "`reset()` method sets STA to value 0"]
196impl crate::Resettable for STA_SPEC {
197 #[inline(always)]
198 fn reset_value() -> Self::Ux {
199 0
200 }
201}