Enum stm32f2::stm32f215::rcc::pllcfgr::PLLP_A

#[repr(u8)]pub enum PLLP_A {
    DIV2,
    DIV4,
    DIV6,
    DIV8,
}

Main PLL (PLL) division factor for main system clock

Value on reset: 0

Variants

DIV2

0: PLLP=2

DIV4

1: PLLP=4

DIV6

2: PLLP=6

DIV8

3: PLLP=8

Trait Implementations

impl Clone for PLLP_A

fn clone(&self) -> PLLP_A

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PLLP_A

impl Debug for PLLP_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq<PLLP_A> for PLLP_A

fn eq(&self, other: &PLLP_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for PLLP_A