Type Definition stm32f2::stm32f215::dma2::hisr::R

type R = R<u32, HISR>;

Reader of register HISR

Implementations

impl R

pub fn tcif7(&self) -> TCIF7_R

Bit 27 - Stream x transfer complete interrupt flag (x=7..4)

pub fn htif7(&self) -> HTIF7_R

Bit 26 - Stream x half transfer interrupt flag (x=7..4)

pub fn teif7(&self) -> TEIF7_R

Bit 25 - Stream x transfer error interrupt flag (x=7..4)

pub fn dmeif7(&self) -> DMEIF7_R

Bit 24 - Stream x direct mode error interrupt flag (x=7..4)

pub fn feif7(&self) -> FEIF7_R

Bit 22 - Stream x FIFO error interrupt flag (x=7..4)

pub fn tcif6(&self) -> TCIF6_R

Bit 21 - Stream x transfer complete interrupt flag (x=7..4)

pub fn htif6(&self) -> HTIF6_R

Bit 20 - Stream x half transfer interrupt flag (x=7..4)

pub fn teif6(&self) -> TEIF6_R

Bit 19 - Stream x transfer error interrupt flag (x=7..4)

pub fn dmeif6(&self) -> DMEIF6_R

Bit 18 - Stream x direct mode error interrupt flag (x=7..4)

pub fn feif6(&self) -> FEIF6_R

Bit 16 - Stream x FIFO error interrupt flag (x=7..4)

pub fn tcif5(&self) -> TCIF5_R

Bit 11 - Stream x transfer complete interrupt flag (x=7..4)

pub fn htif5(&self) -> HTIF5_R

Bit 10 - Stream x half transfer interrupt flag (x=7..4)

pub fn teif5(&self) -> TEIF5_R

Bit 9 - Stream x transfer error interrupt flag (x=7..4)

pub fn dmeif5(&self) -> DMEIF5_R

Bit 8 - Stream x direct mode error interrupt flag (x=7..4)

pub fn feif5(&self) -> FEIF5_R

Bit 6 - Stream x FIFO error interrupt flag (x=7..4)

pub fn tcif4(&self) -> TCIF4_R

Bit 5 - Stream x transfer complete interrupt flag (x=7..4)

pub fn htif4(&self) -> HTIF4_R

Bit 4 - Stream x half transfer interrupt flag (x=7..4)

pub fn teif4(&self) -> TEIF4_R

Bit 3 - Stream x transfer error interrupt flag (x=7..4)

pub fn dmeif4(&self) -> DMEIF4_R

Bit 2 - Stream x direct mode error interrupt flag (x=7..4)

pub fn feif4(&self) -> FEIF4_R

Bit 0 - Stream x FIFO error interrupt flag (x=7..4)