stm32f1xx_hal/rcc/
enable.rs

1use super::*;
2use crate::bb;
3
4macro_rules! bus_enable {
5    ($PER:ident => $bit:literal) => {
6        impl Enable for crate::pac::$PER {
7            #[inline(always)]
8            fn enable(rcc: &mut RCC) {
9                unsafe {
10                    bb::set(Self::Bus::enr(rcc), $bit);
11                }
12                // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
13                cortex_m::asm::dsb();
14            }
15            #[inline(always)]
16            fn disable(rcc: &mut RCC) {
17                unsafe {
18                    bb::clear(Self::Bus::enr(rcc), $bit);
19                }
20            }
21            #[inline(always)]
22            fn is_enabled() -> bool {
23                let rcc = RCC::ptr();
24                (Self::Bus::enr(unsafe { &*rcc }).read().bits() >> $bit) & 0x1 != 0
25            }
26        }
27    };
28}
29
30macro_rules! bus_reset {
31    ($PER:ident => $bit:literal) => {
32        impl Reset for crate::pac::$PER {
33            #[inline(always)]
34            fn reset(rcc: &mut RCC) {
35                let rstr = Self::Bus::rstr(rcc);
36                unsafe {
37                    bb::set(rstr, $bit);
38                    bb::clear(rstr, $bit);
39                }
40            }
41        }
42    };
43}
44
45macro_rules! bus {
46    ($($PER:ident => ($busX:ty, $bit:literal),)+) => {
47        $(
48            impl RccBus for crate::pac::$PER {
49                type Bus = $busX;
50            }
51            bus_enable!($PER => $bit);
52            bus_reset!($PER => $bit);
53        )+
54    }
55}
56
57#[cfg(feature = "stm32f103")]
58bus! {
59    ADC2 => (APB2, 10),
60    CAN => (APB1, 25),
61}
62#[cfg(feature = "connectivity")]
63bus! {
64    ADC2 => (APB2, 10),
65    CAN1 => (APB1, 25),
66    CAN2 => (APB1, 26),
67}
68#[cfg(feature = "has-dac")]
69bus! {
70    DAC => (APB1, 29),
71}
72#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
73bus! {
74    ADC3 => (APB2, 15),
75    UART4 => (APB1, 19),
76    UART5 => (APB1, 20),
77}
78bus! {
79    ADC1 => (APB2, 9),
80    AFIO => (APB2, 0),
81    BKP => (APB1, 27),
82    GPIOA => (APB2, 2),
83    GPIOB => (APB2, 3),
84    GPIOC => (APB2, 4),
85    GPIOD => (APB2, 5),
86    GPIOE => (APB2, 6),
87    I2C1 => (APB1, 21),
88    I2C2 => (APB1, 22),
89    PWR => (APB1, 28),
90    SPI1 => (APB2, 12),
91    SPI2 => (APB1, 14),
92    USART1 => (APB2, 14),
93    USART2 => (APB1, 17),
94    USART3 => (APB1, 18),
95    WWDG => (APB1, 11),
96}
97
98#[cfg(any(feature = "xl", feature = "high"))]
99bus! {
100    GPIOF => (APB2, 7),
101    GPIOG => (APB2, 8),
102}
103
104#[cfg(any(feature = "high", feature = "connectivity"))]
105bus! {
106    SPI3 => (APB1, 15),
107}
108
109impl RccBus for crate::pac::CRC {
110    type Bus = AHB;
111}
112bus_enable! { CRC => 6 }
113impl RccBus for crate::pac::DMA1 {
114    type Bus = AHB;
115}
116bus_enable! { DMA1 => 0 }
117impl RccBus for crate::pac::DMA2 {
118    type Bus = AHB;
119}
120bus_enable! { DMA2 => 1 }
121
122#[cfg(feature = "high")]
123impl RccBus for crate::pac::FSMC {
124    type Bus = AHB;
125}
126#[cfg(feature = "high")]
127bus_enable! { FSMC => 8 }
128
129bus! {
130    TIM2 => (APB1, 0),
131    TIM3 => (APB1, 1),
132}
133
134#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
135bus! {
136    TIM1 => (APB2, 11),
137}
138
139#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
140bus! {
141    TIM6 => (APB1, 4),
142}
143
144#[cfg(any(
145    all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
146    any(feature = "stm32f100", feature = "connectivity")
147))]
148bus! {
149    TIM7 => (APB1, 5),
150}
151
152#[cfg(feature = "stm32f100")]
153bus! {
154    TIM15 => (APB2, 16),
155    TIM16 => (APB2, 17),
156    TIM17 => (APB2, 18),
157}
158
159#[cfg(feature = "medium")]
160bus! {
161    TIM4 => (APB1, 2),
162}
163
164#[cfg(any(feature = "high", feature = "connectivity"))]
165bus! {
166    TIM5 => (APB1, 3),
167}
168
169#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high")))]
170bus! {
171    TIM12 => (APB1, 6),
172    TIM13 => (APB1, 7),
173    TIM14 => (APB1, 8),
174}
175
176#[cfg(all(feature = "stm32f103", feature = "high"))]
177bus! {
178    TIM8 => (APB2, 13),
179}
180
181#[cfg(feature = "xl")]
182bus! {
183    TIM9 => (APB2, 19),
184    TIM10 => (APB2, 20),
185    TIM11 => (APB2, 21),
186}
187
188#[cfg(feature = "stm32f103")] // feature = "stm32f102"
189bus! {
190    USB => (APB1, 23),
191}
stm32f1xx_hal/rcc/enable.rs

stm32f1xx_hal/rcc/
enable.rs
