stm32f103xx/tim2/smcr/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::SMCR {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct ETPR {
47    bits: bool,
48}
49impl ETPR {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bit(&self) -> bool {
53        self.bits
54    }
55    #[doc = r" Returns `true` if the bit is clear (0)"]
56    #[inline]
57    pub fn bit_is_clear(&self) -> bool {
58        !self.bit()
59    }
60    #[doc = r" Returns `true` if the bit is set (1)"]
61    #[inline]
62    pub fn bit_is_set(&self) -> bool {
63        self.bit()
64    }
65}
66#[doc = r" Value of the field"]
67pub struct ECER {
68    bits: bool,
69}
70impl ECER {
71    #[doc = r" Value of the field as raw bits"]
72    #[inline]
73    pub fn bit(&self) -> bool {
74        self.bits
75    }
76    #[doc = r" Returns `true` if the bit is clear (0)"]
77    #[inline]
78    pub fn bit_is_clear(&self) -> bool {
79        !self.bit()
80    }
81    #[doc = r" Returns `true` if the bit is set (1)"]
82    #[inline]
83    pub fn bit_is_set(&self) -> bool {
84        self.bit()
85    }
86}
87#[doc = r" Value of the field"]
88pub struct ETPSR {
89    bits: u8,
90}
91impl ETPSR {
92    #[doc = r" Value of the field as raw bits"]
93    #[inline]
94    pub fn bits(&self) -> u8 {
95        self.bits
96    }
97}
98#[doc = r" Value of the field"]
99pub struct ETFR {
100    bits: u8,
101}
102impl ETFR {
103    #[doc = r" Value of the field as raw bits"]
104    #[inline]
105    pub fn bits(&self) -> u8 {
106        self.bits
107    }
108}
109#[doc = r" Value of the field"]
110pub struct MSMR {
111    bits: bool,
112}
113impl MSMR {
114    #[doc = r" Value of the field as raw bits"]
115    #[inline]
116    pub fn bit(&self) -> bool {
117        self.bits
118    }
119    #[doc = r" Returns `true` if the bit is clear (0)"]
120    #[inline]
121    pub fn bit_is_clear(&self) -> bool {
122        !self.bit()
123    }
124    #[doc = r" Returns `true` if the bit is set (1)"]
125    #[inline]
126    pub fn bit_is_set(&self) -> bool {
127        self.bit()
128    }
129}
130#[doc = "Possible values of the field `TS`"]
131pub type TSR = ::tim1::smcr::TSR;
132#[doc = "Possible values of the field `SMS`"]
133pub type SMSR = ::tim1::smcr::SMSR;
134#[doc = r" Proxy"]
135pub struct _ETPW<'a> {
136    w: &'a mut W,
137}
138impl<'a> _ETPW<'a> {
139    #[doc = r" Sets the field bit"]
140    pub fn set_bit(self) -> &'a mut W {
141        self.bit(true)
142    }
143    #[doc = r" Clears the field bit"]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r" Writes raw bits to the field"]
148    #[inline]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        const MASK: bool = true;
151        const OFFSET: u8 = 15;
152        self.w.bits &= !((MASK as u32) << OFFSET);
153        self.w.bits |= ((value & MASK) as u32) << OFFSET;
154        self.w
155    }
156}
157#[doc = r" Proxy"]
158pub struct _ECEW<'a> {
159    w: &'a mut W,
160}
161impl<'a> _ECEW<'a> {
162    #[doc = r" Sets the field bit"]
163    pub fn set_bit(self) -> &'a mut W {
164        self.bit(true)
165    }
166    #[doc = r" Clears the field bit"]
167    pub fn clear_bit(self) -> &'a mut W {
168        self.bit(false)
169    }
170    #[doc = r" Writes raw bits to the field"]
171    #[inline]
172    pub fn bit(self, value: bool) -> &'a mut W {
173        const MASK: bool = true;
174        const OFFSET: u8 = 14;
175        self.w.bits &= !((MASK as u32) << OFFSET);
176        self.w.bits |= ((value & MASK) as u32) << OFFSET;
177        self.w
178    }
179}
180#[doc = r" Proxy"]
181pub struct _ETPSW<'a> {
182    w: &'a mut W,
183}
184impl<'a> _ETPSW<'a> {
185    #[doc = r" Writes raw bits to the field"]
186    #[inline]
187    pub unsafe fn bits(self, value: u8) -> &'a mut W {
188        const MASK: u8 = 3;
189        const OFFSET: u8 = 12;
190        self.w.bits &= !((MASK as u32) << OFFSET);
191        self.w.bits |= ((value & MASK) as u32) << OFFSET;
192        self.w
193    }
194}
195#[doc = r" Proxy"]
196pub struct _ETFW<'a> {
197    w: &'a mut W,
198}
199impl<'a> _ETFW<'a> {
200    #[doc = r" Writes raw bits to the field"]
201    #[inline]
202    pub unsafe fn bits(self, value: u8) -> &'a mut W {
203        const MASK: u8 = 15;
204        const OFFSET: u8 = 8;
205        self.w.bits &= !((MASK as u32) << OFFSET);
206        self.w.bits |= ((value & MASK) as u32) << OFFSET;
207        self.w
208    }
209}
210#[doc = r" Proxy"]
211pub struct _MSMW<'a> {
212    w: &'a mut W,
213}
214impl<'a> _MSMW<'a> {
215    #[doc = r" Sets the field bit"]
216    pub fn set_bit(self) -> &'a mut W {
217        self.bit(true)
218    }
219    #[doc = r" Clears the field bit"]
220    pub fn clear_bit(self) -> &'a mut W {
221        self.bit(false)
222    }
223    #[doc = r" Writes raw bits to the field"]
224    #[inline]
225    pub fn bit(self, value: bool) -> &'a mut W {
226        const MASK: bool = true;
227        const OFFSET: u8 = 7;
228        self.w.bits &= !((MASK as u32) << OFFSET);
229        self.w.bits |= ((value & MASK) as u32) << OFFSET;
230        self.w
231    }
232}
233#[doc = "Values that can be written to the field `TS`"]
234pub type TSW = ::tim1::smcr::TSW;
235#[doc = r" Proxy"]
236pub struct _TSW<'a> {
237    w: &'a mut W,
238}
239impl<'a> _TSW<'a> {
240    #[doc = r" Writes `variant` to the field"]
241    #[inline]
242    pub fn variant(self, variant: TSW) -> &'a mut W {
243        {
244            self.bits(variant._bits())
245        }
246    }
247    #[doc = "Internal Trigger 0 (ITR0)"]
248    #[inline]
249    pub fn itr0(self) -> &'a mut W {
250        self.variant(::tim1::smcr::TSW::ITR0)
251    }
252    #[doc = "Internal Trigger 1 (ITR1)"]
253    #[inline]
254    pub fn itr1(self) -> &'a mut W {
255        self.variant(::tim1::smcr::TSW::ITR1)
256    }
257    #[doc = "Internal Trigger 2 (ITR2)"]
258    #[inline]
259    pub fn itr2(self) -> &'a mut W {
260        self.variant(::tim1::smcr::TSW::ITR2)
261    }
262    #[doc = "Internal Trigger 3 (ITR3)"]
263    #[inline]
264    pub fn itr3(self) -> &'a mut W {
265        self.variant(::tim1::smcr::TSW::ITR3)
266    }
267    #[doc = "TI1 Edge Detector"]
268    #[inline]
269    pub fn ti1f_ed(self) -> &'a mut W {
270        self.variant(::tim1::smcr::TSW::TI1F_ED)
271    }
272    #[doc = "Filtered Timer Input 1"]
273    #[inline]
274    pub fn ti1fp1(self) -> &'a mut W {
275        self.variant(::tim1::smcr::TSW::TI1FP1)
276    }
277    #[doc = "Filtered Timer Input 2"]
278    #[inline]
279    pub fn ti2fp2(self) -> &'a mut W {
280        self.variant(::tim1::smcr::TSW::TI2FP2)
281    }
282    #[doc = "External Trigger input"]
283    #[inline]
284    pub fn etrf(self) -> &'a mut W {
285        self.variant(::tim1::smcr::TSW::ETRF)
286    }
287    #[doc = r" Writes raw bits to the field"]
288    #[inline]
289    pub fn bits(self, value: u8) -> &'a mut W {
290        const MASK: u8 = 7;
291        const OFFSET: u8 = 4;
292        self.w.bits &= !((MASK as u32) << OFFSET);
293        self.w.bits |= ((value & MASK) as u32) << OFFSET;
294        self.w
295    }
296}
297#[doc = "Values that can be written to the field `SMS`"]
298pub type SMSW = ::tim1::smcr::SMSW;
299#[doc = r" Proxy"]
300pub struct _SMSW<'a> {
301    w: &'a mut W,
302}
303impl<'a> _SMSW<'a> {
304    #[doc = r" Writes `variant` to the field"]
305    #[inline]
306    pub fn variant(self, variant: SMSW) -> &'a mut W {
307        {
308            self.bits(variant._bits())
309        }
310    }
311    #[doc = "Counter disabled"]
312    #[inline]
313    pub fn disabled(self) -> &'a mut W {
314        self.variant(::tim1::smcr::SMSW::DISABLED)
315    }
316    #[doc = "Encoder mode, count up/down on TI2FP1"]
317    #[inline]
318    pub fn encoder_ti2(self) -> &'a mut W {
319        self.variant(::tim1::smcr::SMSW::ENCODERTI2)
320    }
321    #[doc = "Encoder mode, count up/down on TI1FP2"]
322    #[inline]
323    pub fn encoder_ti1(self) -> &'a mut W {
324        self.variant(::tim1::smcr::SMSW::ENCODERTI1)
325    }
326    #[doc = "Encoder mode, count up/down on both TI1FP1 and TI2FP2"]
327    #[inline]
328    pub fn encoder_ti1ti2(self) -> &'a mut W {
329        self.variant(::tim1::smcr::SMSW::ENCODERTI1TI2)
330    }
331    #[doc = "Rising edge of the selected trigger input (TRGI) reinitializes the counter"]
332    #[inline]
333    pub fn reset(self) -> &'a mut W {
334        self.variant(::tim1::smcr::SMSW::RESET)
335    }
336    #[doc = "The counter clock is enabled when the trigger input (TRGI) is high"]
337    #[inline]
338    pub fn gated(self) -> &'a mut W {
339        self.variant(::tim1::smcr::SMSW::GATED)
340    }
341    #[doc = "The counter starts at a rising edge of the trigger TRGI"]
342    #[inline]
343    pub fn trigger(self) -> &'a mut W {
344        self.variant(::tim1::smcr::SMSW::TRIGGER)
345    }
346    #[doc = "Rising edges of the selected trigger (TRGI) clock the counter"]
347    #[inline]
348    pub fn external(self) -> &'a mut W {
349        self.variant(::tim1::smcr::SMSW::EXTERNAL)
350    }
351    #[doc = r" Writes raw bits to the field"]
352    #[inline]
353    pub fn bits(self, value: u8) -> &'a mut W {
354        const MASK: u8 = 7;
355        const OFFSET: u8 = 0;
356        self.w.bits &= !((MASK as u32) << OFFSET);
357        self.w.bits |= ((value & MASK) as u32) << OFFSET;
358        self.w
359    }
360}
361impl R {
362    #[doc = r" Value of the register as raw bits"]
363    #[inline]
364    pub fn bits(&self) -> u32 {
365        self.bits
366    }
367    #[doc = "Bit 15 - External trigger polarity"]
368    #[inline]
369    pub fn etp(&self) -> ETPR {
370        let bits = {
371            const MASK: bool = true;
372            const OFFSET: u8 = 15;
373            ((self.bits >> OFFSET) & MASK as u32) != 0
374        };
375        ETPR { bits }
376    }
377    #[doc = "Bit 14 - External clock enable"]
378    #[inline]
379    pub fn ece(&self) -> ECER {
380        let bits = {
381            const MASK: bool = true;
382            const OFFSET: u8 = 14;
383            ((self.bits >> OFFSET) & MASK as u32) != 0
384        };
385        ECER { bits }
386    }
387    #[doc = "Bits 12:13 - External trigger prescaler"]
388    #[inline]
389    pub fn etps(&self) -> ETPSR {
390        let bits = {
391            const MASK: u8 = 3;
392            const OFFSET: u8 = 12;
393            ((self.bits >> OFFSET) & MASK as u32) as u8
394        };
395        ETPSR { bits }
396    }
397    #[doc = "Bits 8:11 - External trigger filter"]
398    #[inline]
399    pub fn etf(&self) -> ETFR {
400        let bits = {
401            const MASK: u8 = 15;
402            const OFFSET: u8 = 8;
403            ((self.bits >> OFFSET) & MASK as u32) as u8
404        };
405        ETFR { bits }
406    }
407    #[doc = "Bit 7 - Master/Slave mode"]
408    #[inline]
409    pub fn msm(&self) -> MSMR {
410        let bits = {
411            const MASK: bool = true;
412            const OFFSET: u8 = 7;
413            ((self.bits >> OFFSET) & MASK as u32) != 0
414        };
415        MSMR { bits }
416    }
417    #[doc = "Bits 4:6 - Trigger selection"]
418    #[inline]
419    pub fn ts(&self) -> TSR {
420        TSR::_from({
421            const MASK: u8 = 7;
422            const OFFSET: u8 = 4;
423            ((self.bits >> OFFSET) & MASK as u32) as u8
424        })
425    }
426    #[doc = "Bits 0:2 - Slave mode selection"]
427    #[inline]
428    pub fn sms(&self) -> SMSR {
429        SMSR::_from({
430            const MASK: u8 = 7;
431            const OFFSET: u8 = 0;
432            ((self.bits >> OFFSET) & MASK as u32) as u8
433        })
434    }
435}
436impl W {
437    #[doc = r" Reset value of the register"]
438    #[inline]
439    pub fn reset_value() -> W {
440        W { bits: 0 }
441    }
442    #[doc = r" Writes raw bits to the register"]
443    #[inline]
444    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
445        self.bits = bits;
446        self
447    }
448    #[doc = "Bit 15 - External trigger polarity"]
449    #[inline]
450    pub fn etp(&mut self) -> _ETPW {
451        _ETPW { w: self }
452    }
453    #[doc = "Bit 14 - External clock enable"]
454    #[inline]
455    pub fn ece(&mut self) -> _ECEW {
456        _ECEW { w: self }
457    }
458    #[doc = "Bits 12:13 - External trigger prescaler"]
459    #[inline]
460    pub fn etps(&mut self) -> _ETPSW {
461        _ETPSW { w: self }
462    }
463    #[doc = "Bits 8:11 - External trigger filter"]
464    #[inline]
465    pub fn etf(&mut self) -> _ETFW {
466        _ETFW { w: self }
467    }
468    #[doc = "Bit 7 - Master/Slave mode"]
469    #[inline]
470    pub fn msm(&mut self) -> _MSMW {
471        _MSMW { w: self }
472    }
473    #[doc = "Bits 4:6 - Trigger selection"]
474    #[inline]
475    pub fn ts(&mut self) -> _TSW {
476        _TSW { w: self }
477    }
478    #[doc = "Bits 0:2 - Slave mode selection"]
479    #[inline]
480    pub fn sms(&mut self) -> _SMSW {
481        _SMSW { w: self }
482    }
483}
stm32f103xx/tim2/smcr/mod.rs

stm32f103xx/tim2/smcr/
mod.rs
