stm32f103xx/dma1/ccr3/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::CCR3 {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = "Possible values of the field `EN`"]
46pub type ENR = ::rcc::ahbenr::DMA1ENR;
47#[doc = r" Value of the field"]
48pub struct TCIER {
49    bits: bool,
50}
51impl TCIER {
52    #[doc = r" Value of the field as raw bits"]
53    #[inline]
54    pub fn bit(&self) -> bool {
55        self.bits
56    }
57    #[doc = r" Returns `true` if the bit is clear (0)"]
58    #[inline]
59    pub fn bit_is_clear(&self) -> bool {
60        !self.bit()
61    }
62    #[doc = r" Returns `true` if the bit is set (1)"]
63    #[inline]
64    pub fn bit_is_set(&self) -> bool {
65        self.bit()
66    }
67}
68#[doc = r" Value of the field"]
69pub struct HTIER {
70    bits: bool,
71}
72impl HTIER {
73    #[doc = r" Value of the field as raw bits"]
74    #[inline]
75    pub fn bit(&self) -> bool {
76        self.bits
77    }
78    #[doc = r" Returns `true` if the bit is clear (0)"]
79    #[inline]
80    pub fn bit_is_clear(&self) -> bool {
81        !self.bit()
82    }
83    #[doc = r" Returns `true` if the bit is set (1)"]
84    #[inline]
85    pub fn bit_is_set(&self) -> bool {
86        self.bit()
87    }
88}
89#[doc = r" Value of the field"]
90pub struct TEIER {
91    bits: bool,
92}
93impl TEIER {
94    #[doc = r" Value of the field as raw bits"]
95    #[inline]
96    pub fn bit(&self) -> bool {
97        self.bits
98    }
99    #[doc = r" Returns `true` if the bit is clear (0)"]
100    #[inline]
101    pub fn bit_is_clear(&self) -> bool {
102        !self.bit()
103    }
104    #[doc = r" Returns `true` if the bit is set (1)"]
105    #[inline]
106    pub fn bit_is_set(&self) -> bool {
107        self.bit()
108    }
109}
110#[doc = r" Value of the field"]
111pub struct DIRR {
112    bits: bool,
113}
114impl DIRR {
115    #[doc = r" Value of the field as raw bits"]
116    #[inline]
117    pub fn bit(&self) -> bool {
118        self.bits
119    }
120    #[doc = r" Returns `true` if the bit is clear (0)"]
121    #[inline]
122    pub fn bit_is_clear(&self) -> bool {
123        !self.bit()
124    }
125    #[doc = r" Returns `true` if the bit is set (1)"]
126    #[inline]
127    pub fn bit_is_set(&self) -> bool {
128        self.bit()
129    }
130}
131#[doc = r" Value of the field"]
132pub struct CIRCR {
133    bits: bool,
134}
135impl CIRCR {
136    #[doc = r" Value of the field as raw bits"]
137    #[inline]
138    pub fn bit(&self) -> bool {
139        self.bits
140    }
141    #[doc = r" Returns `true` if the bit is clear (0)"]
142    #[inline]
143    pub fn bit_is_clear(&self) -> bool {
144        !self.bit()
145    }
146    #[doc = r" Returns `true` if the bit is set (1)"]
147    #[inline]
148    pub fn bit_is_set(&self) -> bool {
149        self.bit()
150    }
151}
152#[doc = r" Value of the field"]
153pub struct PINCR {
154    bits: bool,
155}
156impl PINCR {
157    #[doc = r" Value of the field as raw bits"]
158    #[inline]
159    pub fn bit(&self) -> bool {
160        self.bits
161    }
162    #[doc = r" Returns `true` if the bit is clear (0)"]
163    #[inline]
164    pub fn bit_is_clear(&self) -> bool {
165        !self.bit()
166    }
167    #[doc = r" Returns `true` if the bit is set (1)"]
168    #[inline]
169    pub fn bit_is_set(&self) -> bool {
170        self.bit()
171    }
172}
173#[doc = r" Value of the field"]
174pub struct MINCR {
175    bits: bool,
176}
177impl MINCR {
178    #[doc = r" Value of the field as raw bits"]
179    #[inline]
180    pub fn bit(&self) -> bool {
181        self.bits
182    }
183    #[doc = r" Returns `true` if the bit is clear (0)"]
184    #[inline]
185    pub fn bit_is_clear(&self) -> bool {
186        !self.bit()
187    }
188    #[doc = r" Returns `true` if the bit is set (1)"]
189    #[inline]
190    pub fn bit_is_set(&self) -> bool {
191        self.bit()
192    }
193}
194#[doc = "Possible values of the field `PSIZE`"]
195pub type PSIZER = ::dma1::ccr1::PSIZER;
196#[doc = "Possible values of the field `MSIZE`"]
197pub type MSIZER = ::dma1::ccr1::PSIZER;
198#[doc = "Possible values of the field `PL`"]
199pub type PLR = ::dma1::ccr1::PLR;
200#[doc = r" Value of the field"]
201pub struct MEM2MEMR {
202    bits: bool,
203}
204impl MEM2MEMR {
205    #[doc = r" Value of the field as raw bits"]
206    #[inline]
207    pub fn bit(&self) -> bool {
208        self.bits
209    }
210    #[doc = r" Returns `true` if the bit is clear (0)"]
211    #[inline]
212    pub fn bit_is_clear(&self) -> bool {
213        !self.bit()
214    }
215    #[doc = r" Returns `true` if the bit is set (1)"]
216    #[inline]
217    pub fn bit_is_set(&self) -> bool {
218        self.bit()
219    }
220}
221#[doc = "Values that can be written to the field `EN`"]
222pub type ENW = ::rcc::ahbenr::DMA1ENW;
223#[doc = r" Proxy"]
224pub struct _ENW<'a> {
225    w: &'a mut W,
226}
227impl<'a> _ENW<'a> {
228    #[doc = r" Writes `variant` to the field"]
229    #[inline]
230    pub fn variant(self, variant: ENW) -> &'a mut W {
231        {
232            self.bit(variant._bits())
233        }
234    }
235    #[doc = "Disabled."]
236    #[inline]
237    pub fn disabled(self) -> &'a mut W {
238        self.variant(::rcc::ahbenr::DMA1ENW::DISABLED)
239    }
240    #[doc = "Enabled."]
241    #[inline]
242    pub fn enabled(self) -> &'a mut W {
243        self.variant(::rcc::ahbenr::DMA1ENW::ENABLED)
244    }
245    #[doc = r" Sets the field bit"]
246    pub fn set_bit(self) -> &'a mut W {
247        self.bit(true)
248    }
249    #[doc = r" Clears the field bit"]
250    pub fn clear_bit(self) -> &'a mut W {
251        self.bit(false)
252    }
253    #[doc = r" Writes raw bits to the field"]
254    #[inline]
255    pub fn bit(self, value: bool) -> &'a mut W {
256        const MASK: bool = true;
257        const OFFSET: u8 = 0;
258        self.w.bits &= !((MASK as u32) << OFFSET);
259        self.w.bits |= ((value & MASK) as u32) << OFFSET;
260        self.w
261    }
262}
263#[doc = r" Proxy"]
264pub struct _TCIEW<'a> {
265    w: &'a mut W,
266}
267impl<'a> _TCIEW<'a> {
268    #[doc = r" Sets the field bit"]
269    pub fn set_bit(self) -> &'a mut W {
270        self.bit(true)
271    }
272    #[doc = r" Clears the field bit"]
273    pub fn clear_bit(self) -> &'a mut W {
274        self.bit(false)
275    }
276    #[doc = r" Writes raw bits to the field"]
277    #[inline]
278    pub fn bit(self, value: bool) -> &'a mut W {
279        const MASK: bool = true;
280        const OFFSET: u8 = 1;
281        self.w.bits &= !((MASK as u32) << OFFSET);
282        self.w.bits |= ((value & MASK) as u32) << OFFSET;
283        self.w
284    }
285}
286#[doc = r" Proxy"]
287pub struct _HTIEW<'a> {
288    w: &'a mut W,
289}
290impl<'a> _HTIEW<'a> {
291    #[doc = r" Sets the field bit"]
292    pub fn set_bit(self) -> &'a mut W {
293        self.bit(true)
294    }
295    #[doc = r" Clears the field bit"]
296    pub fn clear_bit(self) -> &'a mut W {
297        self.bit(false)
298    }
299    #[doc = r" Writes raw bits to the field"]
300    #[inline]
301    pub fn bit(self, value: bool) -> &'a mut W {
302        const MASK: bool = true;
303        const OFFSET: u8 = 2;
304        self.w.bits &= !((MASK as u32) << OFFSET);
305        self.w.bits |= ((value & MASK) as u32) << OFFSET;
306        self.w
307    }
308}
309#[doc = r" Proxy"]
310pub struct _TEIEW<'a> {
311    w: &'a mut W,
312}
313impl<'a> _TEIEW<'a> {
314    #[doc = r" Sets the field bit"]
315    pub fn set_bit(self) -> &'a mut W {
316        self.bit(true)
317    }
318    #[doc = r" Clears the field bit"]
319    pub fn clear_bit(self) -> &'a mut W {
320        self.bit(false)
321    }
322    #[doc = r" Writes raw bits to the field"]
323    #[inline]
324    pub fn bit(self, value: bool) -> &'a mut W {
325        const MASK: bool = true;
326        const OFFSET: u8 = 3;
327        self.w.bits &= !((MASK as u32) << OFFSET);
328        self.w.bits |= ((value & MASK) as u32) << OFFSET;
329        self.w
330    }
331}
332#[doc = r" Proxy"]
333pub struct _DIRW<'a> {
334    w: &'a mut W,
335}
336impl<'a> _DIRW<'a> {
337    #[doc = r" Sets the field bit"]
338    pub fn set_bit(self) -> &'a mut W {
339        self.bit(true)
340    }
341    #[doc = r" Clears the field bit"]
342    pub fn clear_bit(self) -> &'a mut W {
343        self.bit(false)
344    }
345    #[doc = r" Writes raw bits to the field"]
346    #[inline]
347    pub fn bit(self, value: bool) -> &'a mut W {
348        const MASK: bool = true;
349        const OFFSET: u8 = 4;
350        self.w.bits &= !((MASK as u32) << OFFSET);
351        self.w.bits |= ((value & MASK) as u32) << OFFSET;
352        self.w
353    }
354}
355#[doc = r" Proxy"]
356pub struct _CIRCW<'a> {
357    w: &'a mut W,
358}
359impl<'a> _CIRCW<'a> {
360    #[doc = r" Sets the field bit"]
361    pub fn set_bit(self) -> &'a mut W {
362        self.bit(true)
363    }
364    #[doc = r" Clears the field bit"]
365    pub fn clear_bit(self) -> &'a mut W {
366        self.bit(false)
367    }
368    #[doc = r" Writes raw bits to the field"]
369    #[inline]
370    pub fn bit(self, value: bool) -> &'a mut W {
371        const MASK: bool = true;
372        const OFFSET: u8 = 5;
373        self.w.bits &= !((MASK as u32) << OFFSET);
374        self.w.bits |= ((value & MASK) as u32) << OFFSET;
375        self.w
376    }
377}
378#[doc = r" Proxy"]
379pub struct _PINCW<'a> {
380    w: &'a mut W,
381}
382impl<'a> _PINCW<'a> {
383    #[doc = r" Sets the field bit"]
384    pub fn set_bit(self) -> &'a mut W {
385        self.bit(true)
386    }
387    #[doc = r" Clears the field bit"]
388    pub fn clear_bit(self) -> &'a mut W {
389        self.bit(false)
390    }
391    #[doc = r" Writes raw bits to the field"]
392    #[inline]
393    pub fn bit(self, value: bool) -> &'a mut W {
394        const MASK: bool = true;
395        const OFFSET: u8 = 6;
396        self.w.bits &= !((MASK as u32) << OFFSET);
397        self.w.bits |= ((value & MASK) as u32) << OFFSET;
398        self.w
399    }
400}
401#[doc = r" Proxy"]
402pub struct _MINCW<'a> {
403    w: &'a mut W,
404}
405impl<'a> _MINCW<'a> {
406    #[doc = r" Sets the field bit"]
407    pub fn set_bit(self) -> &'a mut W {
408        self.bit(true)
409    }
410    #[doc = r" Clears the field bit"]
411    pub fn clear_bit(self) -> &'a mut W {
412        self.bit(false)
413    }
414    #[doc = r" Writes raw bits to the field"]
415    #[inline]
416    pub fn bit(self, value: bool) -> &'a mut W {
417        const MASK: bool = true;
418        const OFFSET: u8 = 7;
419        self.w.bits &= !((MASK as u32) << OFFSET);
420        self.w.bits |= ((value & MASK) as u32) << OFFSET;
421        self.w
422    }
423}
424#[doc = "Values that can be written to the field `PSIZE`"]
425pub type PSIZEW = ::dma1::ccr1::PSIZEW;
426#[doc = r" Proxy"]
427pub struct _PSIZEW<'a> {
428    w: &'a mut W,
429}
430impl<'a> _PSIZEW<'a> {
431    #[doc = r" Writes `variant` to the field"]
432    #[inline]
433    pub fn variant(self, variant: PSIZEW) -> &'a mut W {
434        unsafe { self.bits(variant._bits()) }
435    }
436    #[doc = "8-bits"]
437    #[inline]
438    pub fn bit8(self) -> &'a mut W {
439        self.variant(::dma1::ccr1::PSIZEW::BIT8)
440    }
441    #[doc = "16-bits"]
442    #[inline]
443    pub fn bit16(self) -> &'a mut W {
444        self.variant(::dma1::ccr1::PSIZEW::BIT16)
445    }
446    #[doc = "32-bits"]
447    #[inline]
448    pub fn bit32(self) -> &'a mut W {
449        self.variant(::dma1::ccr1::PSIZEW::BIT32)
450    }
451    #[doc = r" Writes raw bits to the field"]
452    #[inline]
453    pub unsafe fn bits(self, value: u8) -> &'a mut W {
454        const MASK: u8 = 3;
455        const OFFSET: u8 = 8;
456        self.w.bits &= !((MASK as u32) << OFFSET);
457        self.w.bits |= ((value & MASK) as u32) << OFFSET;
458        self.w
459    }
460}
461#[doc = "Values that can be written to the field `MSIZE`"]
462pub type MSIZEW = ::dma1::ccr1::PSIZEW;
463#[doc = r" Proxy"]
464pub struct _MSIZEW<'a> {
465    w: &'a mut W,
466}
467impl<'a> _MSIZEW<'a> {
468    #[doc = r" Writes `variant` to the field"]
469    #[inline]
470    pub fn variant(self, variant: MSIZEW) -> &'a mut W {
471        unsafe { self.bits(variant._bits()) }
472    }
473    #[doc = "8-bits"]
474    #[inline]
475    pub fn bit8(self) -> &'a mut W {
476        self.variant(::dma1::ccr1::PSIZEW::BIT8)
477    }
478    #[doc = "16-bits"]
479    #[inline]
480    pub fn bit16(self) -> &'a mut W {
481        self.variant(::dma1::ccr1::PSIZEW::BIT16)
482    }
483    #[doc = "32-bits"]
484    #[inline]
485    pub fn bit32(self) -> &'a mut W {
486        self.variant(::dma1::ccr1::PSIZEW::BIT32)
487    }
488    #[doc = r" Writes raw bits to the field"]
489    #[inline]
490    pub unsafe fn bits(self, value: u8) -> &'a mut W {
491        const MASK: u8 = 3;
492        const OFFSET: u8 = 10;
493        self.w.bits &= !((MASK as u32) << OFFSET);
494        self.w.bits |= ((value & MASK) as u32) << OFFSET;
495        self.w
496    }
497}
498#[doc = "Values that can be written to the field `PL`"]
499pub type PLW = ::dma1::ccr1::PLW;
500#[doc = r" Proxy"]
501pub struct _PLW<'a> {
502    w: &'a mut W,
503}
504impl<'a> _PLW<'a> {
505    #[doc = r" Writes `variant` to the field"]
506    #[inline]
507    pub fn variant(self, variant: PLW) -> &'a mut W {
508        {
509            self.bits(variant._bits())
510        }
511    }
512    #[doc = "Low"]
513    #[inline]
514    pub fn low(self) -> &'a mut W {
515        self.variant(::dma1::ccr1::PLW::LOW)
516    }
517    #[doc = "Medium"]
518    #[inline]
519    pub fn medium(self) -> &'a mut W {
520        self.variant(::dma1::ccr1::PLW::MEDIUM)
521    }
522    #[doc = "High"]
523    #[inline]
524    pub fn high(self) -> &'a mut W {
525        self.variant(::dma1::ccr1::PLW::HIGH)
526    }
527    #[doc = "Very High"]
528    #[inline]
529    pub fn very_high(self) -> &'a mut W {
530        self.variant(::dma1::ccr1::PLW::VERYHIGH)
531    }
532    #[doc = r" Writes raw bits to the field"]
533    #[inline]
534    pub fn bits(self, value: u8) -> &'a mut W {
535        const MASK: u8 = 3;
536        const OFFSET: u8 = 12;
537        self.w.bits &= !((MASK as u32) << OFFSET);
538        self.w.bits |= ((value & MASK) as u32) << OFFSET;
539        self.w
540    }
541}
542#[doc = r" Proxy"]
543pub struct _MEM2MEMW<'a> {
544    w: &'a mut W,
545}
546impl<'a> _MEM2MEMW<'a> {
547    #[doc = r" Sets the field bit"]
548    pub fn set_bit(self) -> &'a mut W {
549        self.bit(true)
550    }
551    #[doc = r" Clears the field bit"]
552    pub fn clear_bit(self) -> &'a mut W {
553        self.bit(false)
554    }
555    #[doc = r" Writes raw bits to the field"]
556    #[inline]
557    pub fn bit(self, value: bool) -> &'a mut W {
558        const MASK: bool = true;
559        const OFFSET: u8 = 14;
560        self.w.bits &= !((MASK as u32) << OFFSET);
561        self.w.bits |= ((value & MASK) as u32) << OFFSET;
562        self.w
563    }
564}
565impl R {
566    #[doc = r" Value of the register as raw bits"]
567    #[inline]
568    pub fn bits(&self) -> u32 {
569        self.bits
570    }
571    #[doc = "Bit 0 - Channel enable"]
572    #[inline]
573    pub fn en(&self) -> ENR {
574        ENR::_from({
575            const MASK: bool = true;
576            const OFFSET: u8 = 0;
577            ((self.bits >> OFFSET) & MASK as u32) != 0
578        })
579    }
580    #[doc = "Bit 1 - Transfer complete interrupt enable"]
581    #[inline]
582    pub fn tcie(&self) -> TCIER {
583        let bits = {
584            const MASK: bool = true;
585            const OFFSET: u8 = 1;
586            ((self.bits >> OFFSET) & MASK as u32) != 0
587        };
588        TCIER { bits }
589    }
590    #[doc = "Bit 2 - Half Transfer interrupt enable"]
591    #[inline]
592    pub fn htie(&self) -> HTIER {
593        let bits = {
594            const MASK: bool = true;
595            const OFFSET: u8 = 2;
596            ((self.bits >> OFFSET) & MASK as u32) != 0
597        };
598        HTIER { bits }
599    }
600    #[doc = "Bit 3 - Transfer error interrupt enable"]
601    #[inline]
602    pub fn teie(&self) -> TEIER {
603        let bits = {
604            const MASK: bool = true;
605            const OFFSET: u8 = 3;
606            ((self.bits >> OFFSET) & MASK as u32) != 0
607        };
608        TEIER { bits }
609    }
610    #[doc = "Bit 4 - Data transfer direction"]
611    #[inline]
612    pub fn dir(&self) -> DIRR {
613        let bits = {
614            const MASK: bool = true;
615            const OFFSET: u8 = 4;
616            ((self.bits >> OFFSET) & MASK as u32) != 0
617        };
618        DIRR { bits }
619    }
620    #[doc = "Bit 5 - Circular mode"]
621    #[inline]
622    pub fn circ(&self) -> CIRCR {
623        let bits = {
624            const MASK: bool = true;
625            const OFFSET: u8 = 5;
626            ((self.bits >> OFFSET) & MASK as u32) != 0
627        };
628        CIRCR { bits }
629    }
630    #[doc = "Bit 6 - Peripheral increment mode"]
631    #[inline]
632    pub fn pinc(&self) -> PINCR {
633        let bits = {
634            const MASK: bool = true;
635            const OFFSET: u8 = 6;
636            ((self.bits >> OFFSET) & MASK as u32) != 0
637        };
638        PINCR { bits }
639    }
640    #[doc = "Bit 7 - Memory increment mode"]
641    #[inline]
642    pub fn minc(&self) -> MINCR {
643        let bits = {
644            const MASK: bool = true;
645            const OFFSET: u8 = 7;
646            ((self.bits >> OFFSET) & MASK as u32) != 0
647        };
648        MINCR { bits }
649    }
650    #[doc = "Bits 8:9 - Peripheral size"]
651    #[inline]
652    pub fn psize(&self) -> PSIZER {
653        PSIZER::_from({
654            const MASK: u8 = 3;
655            const OFFSET: u8 = 8;
656            ((self.bits >> OFFSET) & MASK as u32) as u8
657        })
658    }
659    #[doc = "Bits 10:11 - Memory size"]
660    #[inline]
661    pub fn msize(&self) -> MSIZER {
662        MSIZER::_from({
663            const MASK: u8 = 3;
664            const OFFSET: u8 = 10;
665            ((self.bits >> OFFSET) & MASK as u32) as u8
666        })
667    }
668    #[doc = "Bits 12:13 - Channel Priority level"]
669    #[inline]
670    pub fn pl(&self) -> PLR {
671        PLR::_from({
672            const MASK: u8 = 3;
673            const OFFSET: u8 = 12;
674            ((self.bits >> OFFSET) & MASK as u32) as u8
675        })
676    }
677    #[doc = "Bit 14 - Memory to memory mode"]
678    #[inline]
679    pub fn mem2mem(&self) -> MEM2MEMR {
680        let bits = {
681            const MASK: bool = true;
682            const OFFSET: u8 = 14;
683            ((self.bits >> OFFSET) & MASK as u32) != 0
684        };
685        MEM2MEMR { bits }
686    }
687}
688impl W {
689    #[doc = r" Reset value of the register"]
690    #[inline]
691    pub fn reset_value() -> W {
692        W { bits: 0 }
693    }
694    #[doc = r" Writes raw bits to the register"]
695    #[inline]
696    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
697        self.bits = bits;
698        self
699    }
700    #[doc = "Bit 0 - Channel enable"]
701    #[inline]
702    pub fn en(&mut self) -> _ENW {
703        _ENW { w: self }
704    }
705    #[doc = "Bit 1 - Transfer complete interrupt enable"]
706    #[inline]
707    pub fn tcie(&mut self) -> _TCIEW {
708        _TCIEW { w: self }
709    }
710    #[doc = "Bit 2 - Half Transfer interrupt enable"]
711    #[inline]
712    pub fn htie(&mut self) -> _HTIEW {
713        _HTIEW { w: self }
714    }
715    #[doc = "Bit 3 - Transfer error interrupt enable"]
716    #[inline]
717    pub fn teie(&mut self) -> _TEIEW {
718        _TEIEW { w: self }
719    }
720    #[doc = "Bit 4 - Data transfer direction"]
721    #[inline]
722    pub fn dir(&mut self) -> _DIRW {
723        _DIRW { w: self }
724    }
725    #[doc = "Bit 5 - Circular mode"]
726    #[inline]
727    pub fn circ(&mut self) -> _CIRCW {
728        _CIRCW { w: self }
729    }
730    #[doc = "Bit 6 - Peripheral increment mode"]
731    #[inline]
732    pub fn pinc(&mut self) -> _PINCW {
733        _PINCW { w: self }
734    }
735    #[doc = "Bit 7 - Memory increment mode"]
736    #[inline]
737    pub fn minc(&mut self) -> _MINCW {
738        _MINCW { w: self }
739    }
740    #[doc = "Bits 8:9 - Peripheral size"]
741    #[inline]
742    pub fn psize(&mut self) -> _PSIZEW {
743        _PSIZEW { w: self }
744    }
745    #[doc = "Bits 10:11 - Memory size"]
746    #[inline]
747    pub fn msize(&mut self) -> _MSIZEW {
748        _MSIZEW { w: self }
749    }
750    #[doc = "Bits 12:13 - Channel Priority level"]
751    #[inline]
752    pub fn pl(&mut self) -> _PLW {
753        _PLW { w: self }
754    }
755    #[doc = "Bit 14 - Memory to memory mode"]
756    #[inline]
757    pub fn mem2mem(&mut self) -> _MEM2MEMW {
758        _MEM2MEMW { w: self }
759    }
760}
stm32f103xx/dma1/ccr3/mod.rs

stm32f103xx/dma1/ccr3/
mod.rs
