stm32f103xx/dac/
mod.rs

1#[doc = r" Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - Control register (DAC_CR)"]
5    pub cr: CR,
6    #[doc = "0x04 - DAC software trigger register (DAC_SWTRIGR)"]
7    pub swtrigr: SWTRIGR,
8    #[doc = "0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)"]
9    pub dhr12r1: DHR12R1,
10    #[doc = "0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)"]
11    pub dhr12l1: DHR12L1,
12    #[doc = "0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)"]
13    pub dhr8r1: DHR8R1,
14    #[doc = "0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)"]
15    pub dhr12r2: DHR12R2,
16    #[doc = "0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)"]
17    pub dhr12l2: DHR12L2,
18    #[doc = "0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)"]
19    pub dhr8r2: DHR8R2,
20    #[doc = "0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved"]
21    pub dhr12rd: DHR12RD,
22    #[doc = "0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved"]
23    pub dhr12ld: DHR12LD,
24    #[doc = "0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved"]
25    pub dhr8rd: DHR8RD,
26    #[doc = "0x2c - DAC channel1 data output register (DAC_DOR1)"]
27    pub dor1: DOR1,
28    #[doc = "0x30 - DAC channel2 data output register (DAC_DOR2)"]
29    pub dor2: DOR2,
30}
31#[doc = "Control register (DAC_CR)"]
32pub struct CR {
33    register: ::vcell::VolatileCell<u32>,
34}
35#[doc = "Control register (DAC_CR)"]
36pub mod cr;
37#[doc = "DAC software trigger register (DAC_SWTRIGR)"]
38pub struct SWTRIGR {
39    register: ::vcell::VolatileCell<u32>,
40}
41#[doc = "DAC software trigger register (DAC_SWTRIGR)"]
42pub mod swtrigr;
43#[doc = "DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)"]
44pub struct DHR12R1 {
45    register: ::vcell::VolatileCell<u32>,
46}
47#[doc = "DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)"]
48pub mod dhr12r1;
49#[doc = "DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)"]
50pub struct DHR12L1 {
51    register: ::vcell::VolatileCell<u32>,
52}
53#[doc = "DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)"]
54pub mod dhr12l1;
55#[doc = "DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)"]
56pub struct DHR8R1 {
57    register: ::vcell::VolatileCell<u32>,
58}
59#[doc = "DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)"]
60pub mod dhr8r1;
61#[doc = "DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)"]
62pub struct DHR12R2 {
63    register: ::vcell::VolatileCell<u32>,
64}
65#[doc = "DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)"]
66pub mod dhr12r2;
67#[doc = "DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)"]
68pub struct DHR12L2 {
69    register: ::vcell::VolatileCell<u32>,
70}
71#[doc = "DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)"]
72pub mod dhr12l2;
73#[doc = "DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)"]
74pub struct DHR8R2 {
75    register: ::vcell::VolatileCell<u32>,
76}
77#[doc = "DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)"]
78pub mod dhr8r2;
79#[doc = "Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved"]
80pub struct DHR12RD {
81    register: ::vcell::VolatileCell<u32>,
82}
83#[doc = "Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved"]
84pub mod dhr12rd;
85#[doc = "DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved"]
86pub struct DHR12LD {
87    register: ::vcell::VolatileCell<u32>,
88}
89#[doc = "DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved"]
90pub mod dhr12ld;
91#[doc = "DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved"]
92pub struct DHR8RD {
93    register: ::vcell::VolatileCell<u32>,
94}
95#[doc = "DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved"]
96pub mod dhr8rd;
97#[doc = "DAC channel1 data output register (DAC_DOR1)"]
98pub struct DOR1 {
99    register: ::vcell::VolatileCell<u32>,
100}
101#[doc = "DAC channel1 data output register (DAC_DOR1)"]
102pub mod dor1;
103#[doc = "DAC channel2 data output register (DAC_DOR2)"]
104pub struct DOR2 {
105    register: ::vcell::VolatileCell<u32>,
106}
107#[doc = "DAC channel2 data output register (DAC_DOR2)"]
108pub mod dor2;
stm32f103xx/dac/mod.rs

stm32f103xx/dac/
mod.rs
