Struct stm32f103xx::dac::RegisterBlock

pub struct RegisterBlock {
    pub cr: Cr,
    pub swtrigr: Swtrigr,
    pub dhr12r1: Dhr12r1,
    pub dhr12l1: Dhr12l1,
    pub dhr8r1: Dhr8r1,
    pub dhr12r2: Dhr12r2,
    pub dhr12l2: Dhr12l2,
    pub dhr8r2: Dhr8r2,
    pub dhr12rd: Dhr12rd,
    pub dhr12ld: Dhr12ld,
    pub dhr8rd: Dhr8rd,
    pub dor1: Dor1,
    pub dor2: Dor2,
}

Register block

Fields

cr: Cr

0x00 - Control register (DAC_CR)

swtrigr: Swtrigr

0x04 - DAC software trigger register (DAC_SWTRIGR)

dhr12r1: Dhr12r1

0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

dhr12l1: Dhr12l1

0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

dhr8r1: Dhr8r1

0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

dhr12r2: Dhr12r2

0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

dhr12l2: Dhr12l2

0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

dhr8r2: Dhr8r2

0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

dhr12rd: Dhr12rd

0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

dhr12ld: Dhr12ld

0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

dhr8rd: Dhr8rd

0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

dor1: Dor1

0x2c - DAC channel1 data output register (DAC_DOR1)

dor2: Dor2

0x30 - DAC channel2 data output register (DAC_DOR2)