1#![doc = "Peripheral access API for STM32F103 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![no_std]
5#![cfg_attr(docsrs, feature(doc_cfg))]
6#[doc = r"Number available in the NVIC for configuring priority"]
7pub const NVIC_PRIO_BITS: u8 = 4;
8#[allow(unused_imports)]
9use generic::*;
10#[doc = r"Common register and bit access and modify traits"]
11pub mod generic;
12#[cfg(feature = "rt")]
13extern "C" {
14 fn WWDG();
15 fn PVD();
16 fn TAMPER();
17 fn RTC();
18 fn FLASH();
19 fn RCC();
20 fn EXTI0();
21 fn EXTI1();
22 fn EXTI2();
23 fn EXTI3();
24 fn EXTI4();
25 fn DMA1_Channel1();
26 fn DMA1_Channel2();
27 fn DMA1_Channel3();
28 fn DMA1_Channel4();
29 fn DMA1_Channel5();
30 fn DMA1_Channel6();
31 fn DMA1_Channel7();
32 fn ADC1_2();
33 fn USB_HP_CAN_TX();
34 fn USB_LP_CAN_RX0();
35 fn CAN_RX1();
36 fn CAN_SCE();
37 fn EXTI9_5();
38 fn TIM1_BRK();
39 fn TIM1_UP();
40 fn TIM1_TRG_COM();
41 fn TIM1_CC();
42 fn TIM2();
43 fn TIM3();
44 fn TIM4();
45 fn I2C1_EV();
46 fn I2C1_ER();
47 fn I2C2_EV();
48 fn I2C2_ER();
49 fn SPI1();
50 fn SPI2();
51 fn USART1();
52 fn USART2();
53 fn USART3();
54 fn EXTI15_10();
55 fn RTCAlarm();
56 fn TIM8_BRK();
57 fn TIM8_UP();
58 fn TIM8_TRG_COM();
59 fn TIM8_CC();
60 fn ADC3();
61 fn FSMC();
62 fn SDIO();
63 fn TIM5();
64 fn SPI3();
65 fn UART4();
66 fn UART5();
67 fn TIM6();
68 fn TIM7();
69 fn DMA2_Channel1();
70 fn DMA2_Channel2();
71 fn DMA2_Channel3();
72 fn DMA2_Channel4_5();
73}
74#[doc(hidden)]
75#[repr(C)]
76pub union Vector {
77 _handler: unsafe extern "C" fn(),
78 _reserved: u32,
79}
80#[cfg(feature = "rt")]
81#[doc(hidden)]
82#[link_section = ".vector_table.interrupts"]
83#[no_mangle]
84pub static __INTERRUPTS: [Vector; 60] = [
85 Vector { _handler: WWDG },
86 Vector { _handler: PVD },
87 Vector { _handler: TAMPER },
88 Vector { _handler: RTC },
89 Vector { _handler: FLASH },
90 Vector { _handler: RCC },
91 Vector { _handler: EXTI0 },
92 Vector { _handler: EXTI1 },
93 Vector { _handler: EXTI2 },
94 Vector { _handler: EXTI3 },
95 Vector { _handler: EXTI4 },
96 Vector {
97 _handler: DMA1_Channel1,
98 },
99 Vector {
100 _handler: DMA1_Channel2,
101 },
102 Vector {
103 _handler: DMA1_Channel3,
104 },
105 Vector {
106 _handler: DMA1_Channel4,
107 },
108 Vector {
109 _handler: DMA1_Channel5,
110 },
111 Vector {
112 _handler: DMA1_Channel6,
113 },
114 Vector {
115 _handler: DMA1_Channel7,
116 },
117 Vector { _handler: ADC1_2 },
118 Vector {
119 _handler: USB_HP_CAN_TX,
120 },
121 Vector {
122 _handler: USB_LP_CAN_RX0,
123 },
124 Vector { _handler: CAN_RX1 },
125 Vector { _handler: CAN_SCE },
126 Vector { _handler: EXTI9_5 },
127 Vector { _handler: TIM1_BRK },
128 Vector { _handler: TIM1_UP },
129 Vector {
130 _handler: TIM1_TRG_COM,
131 },
132 Vector { _handler: TIM1_CC },
133 Vector { _handler: TIM2 },
134 Vector { _handler: TIM3 },
135 Vector { _handler: TIM4 },
136 Vector { _handler: I2C1_EV },
137 Vector { _handler: I2C1_ER },
138 Vector { _handler: I2C2_EV },
139 Vector { _handler: I2C2_ER },
140 Vector { _handler: SPI1 },
141 Vector { _handler: SPI2 },
142 Vector { _handler: USART1 },
143 Vector { _handler: USART2 },
144 Vector { _handler: USART3 },
145 Vector {
146 _handler: EXTI15_10,
147 },
148 Vector { _handler: RTCAlarm },
149 Vector { _reserved: 0 },
150 Vector { _handler: TIM8_BRK },
151 Vector { _handler: TIM8_UP },
152 Vector {
153 _handler: TIM8_TRG_COM,
154 },
155 Vector { _handler: TIM8_CC },
156 Vector { _handler: ADC3 },
157 Vector { _handler: FSMC },
158 Vector { _handler: SDIO },
159 Vector { _handler: TIM5 },
160 Vector { _handler: SPI3 },
161 Vector { _handler: UART4 },
162 Vector { _handler: UART5 },
163 Vector { _handler: TIM6 },
164 Vector { _handler: TIM7 },
165 Vector {
166 _handler: DMA2_Channel1,
167 },
168 Vector {
169 _handler: DMA2_Channel2,
170 },
171 Vector {
172 _handler: DMA2_Channel3,
173 },
174 Vector {
175 _handler: DMA2_Channel4_5,
176 },
177];
178#[doc = r"Enumeration of all the interrupts."]
179#[derive(Copy, Clone, Debug, PartialEq, Eq)]
180#[repr(u16)]
181pub enum Interrupt {
182 #[doc = "0 - Window Watchdog interrupt"]
183 WWDG = 0,
184 #[doc = "1 - PVD through EXTI line detection interrupt"]
185 PVD = 1,
186 #[doc = "2 - Tamper interrupt"]
187 TAMPER = 2,
188 #[doc = "3 - RTC global interrupt"]
189 RTC = 3,
190 #[doc = "4 - Flash global interrupt"]
191 FLASH = 4,
192 #[doc = "5 - RCC global interrupt"]
193 RCC = 5,
194 #[doc = "6 - EXTI Line0 interrupt"]
195 EXTI0 = 6,
196 #[doc = "7 - EXTI Line1 interrupt"]
197 EXTI1 = 7,
198 #[doc = "8 - EXTI Line2 interrupt"]
199 EXTI2 = 8,
200 #[doc = "9 - EXTI Line3 interrupt"]
201 EXTI3 = 9,
202 #[doc = "10 - EXTI Line4 interrupt"]
203 EXTI4 = 10,
204 #[doc = "11 - DMA1 Channel1 global interrupt"]
205 DMA1_Channel1 = 11,
206 #[doc = "12 - DMA1 Channel2 global interrupt"]
207 DMA1_Channel2 = 12,
208 #[doc = "13 - DMA1 Channel3 global interrupt"]
209 DMA1_Channel3 = 13,
210 #[doc = "14 - DMA1 Channel4 global interrupt"]
211 DMA1_Channel4 = 14,
212 #[doc = "15 - DMA1 Channel5 global interrupt"]
213 DMA1_Channel5 = 15,
214 #[doc = "16 - DMA1 Channel6 global interrupt"]
215 DMA1_Channel6 = 16,
216 #[doc = "17 - DMA1 Channel7 global interrupt"]
217 DMA1_Channel7 = 17,
218 #[doc = "18 - ADC1 and ADC2 global interrupt"]
219 ADC1_2 = 18,
220 #[doc = "19 - USB High Priority or CAN TX interrupts"]
221 USB_HP_CAN_TX = 19,
222 #[doc = "20 - USB Low Priority or CAN RX0 interrupts"]
223 USB_LP_CAN_RX0 = 20,
224 #[doc = "21 - CAN RX1 interrupt"]
225 CAN_RX1 = 21,
226 #[doc = "22 - CAN SCE interrupt"]
227 CAN_SCE = 22,
228 #[doc = "23 - EXTI Line\\[9:5\\] interrupts"]
229 EXTI9_5 = 23,
230 #[doc = "24 - TIM1 Break interrupt"]
231 TIM1_BRK = 24,
232 #[doc = "25 - TIM1 Update interrupt"]
233 TIM1_UP = 25,
234 #[doc = "26 - TIM1 Trigger and Commutation interrupts"]
235 TIM1_TRG_COM = 26,
236 #[doc = "27 - TIM1 Capture Compare interrupt"]
237 TIM1_CC = 27,
238 #[doc = "28 - TIM2 global interrupt"]
239 TIM2 = 28,
240 #[doc = "29 - TIM3 global interrupt"]
241 TIM3 = 29,
242 #[doc = "30 - TIM4 global interrupt"]
243 TIM4 = 30,
244 #[doc = "31 - I2C1 event interrupt"]
245 I2C1_EV = 31,
246 #[doc = "32 - I2C1 error interrupt"]
247 I2C1_ER = 32,
248 #[doc = "33 - I2C2 event interrupt"]
249 I2C2_EV = 33,
250 #[doc = "34 - I2C2 error interrupt"]
251 I2C2_ER = 34,
252 #[doc = "35 - SPI1 global interrupt"]
253 SPI1 = 35,
254 #[doc = "36 - SPI2 global interrupt"]
255 SPI2 = 36,
256 #[doc = "37 - USART1 global interrupt"]
257 USART1 = 37,
258 #[doc = "38 - USART2 global interrupt"]
259 USART2 = 38,
260 #[doc = "39 - USART3 global interrupt"]
261 USART3 = 39,
262 #[doc = "40 - EXTI Line\\[15:10\\] interrupts"]
263 EXTI15_10 = 40,
264 #[doc = "41 - RTC Alarms through EXTI line interrupt"]
265 RTCAlarm = 41,
266 #[doc = "43 - TIM8 Break interrupt"]
267 TIM8_BRK = 43,
268 #[doc = "44 - TIM8 Update interrupt"]
269 TIM8_UP = 44,
270 #[doc = "45 - TIM8 Trigger and Commutation interrupts"]
271 TIM8_TRG_COM = 45,
272 #[doc = "46 - TIM8 Capture Compare interrupt"]
273 TIM8_CC = 46,
274 #[doc = "47 - ADC3 global interrupt"]
275 ADC3 = 47,
276 #[doc = "48 - FSMC global interrupt"]
277 FSMC = 48,
278 #[doc = "49 - SDIO global interrupt"]
279 SDIO = 49,
280 #[doc = "50 - TIM5 global interrupt"]
281 TIM5 = 50,
282 #[doc = "51 - SPI3 global interrupt"]
283 SPI3 = 51,
284 #[doc = "52 - UART4 global interrupt"]
285 UART4 = 52,
286 #[doc = "53 - UART5 global interrupt"]
287 UART5 = 53,
288 #[doc = "54 - TIM6 global interrupt"]
289 TIM6 = 54,
290 #[doc = "55 - TIM7 global interrupt"]
291 TIM7 = 55,
292 #[doc = "56 - DMA2 Channel1 global interrupt"]
293 DMA2_Channel1 = 56,
294 #[doc = "57 - DMA2 Channel2 global interrupt"]
295 DMA2_Channel2 = 57,
296 #[doc = "58 - DMA2 Channel3 global interrupt"]
297 DMA2_Channel3 = 58,
298 #[doc = "59 - DMA2 Channel4 and DMA2 Channel5 global interrupt"]
299 DMA2_Channel4_5 = 59,
300}
301unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
302 #[inline(always)]
303 fn number(self) -> u16 {
304 self as u16
305 }
306}
307#[doc = "Flexible static memory controller"]
308pub type Fsmc = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
309impl core::fmt::Debug for Fsmc {
310 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
311 f.debug_struct("Fsmc").finish()
312 }
313}
314#[doc = "Flexible static memory controller"]
315pub mod fsmc;
316#[doc = "Power control"]
317pub type Pwr = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
318impl core::fmt::Debug for Pwr {
319 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
320 f.debug_struct("Pwr").finish()
321 }
322}
323#[doc = "Power control"]
324pub mod pwr;
325#[doc = "Reset and clock control"]
326pub type Rcc = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
327impl core::fmt::Debug for Rcc {
328 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
329 f.debug_struct("Rcc").finish()
330 }
331}
332#[doc = "Reset and clock control"]
333pub mod rcc;
334#[doc = "General purpose I/O"]
335pub type Gpioa = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
336impl core::fmt::Debug for Gpioa {
337 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
338 f.debug_struct("Gpioa").finish()
339 }
340}
341#[doc = "General purpose I/O"]
342pub mod gpioa;
343#[doc = "General purpose I/O"]
344pub type Gpiob = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
345impl core::fmt::Debug for Gpiob {
346 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
347 f.debug_struct("Gpiob").finish()
348 }
349}
350#[doc = "General purpose I/O"]
351pub use self::gpioa as gpiob;
352#[doc = "General purpose I/O"]
353pub type Gpioc = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
354impl core::fmt::Debug for Gpioc {
355 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
356 f.debug_struct("Gpioc").finish()
357 }
358}
359#[doc = "General purpose I/O"]
360pub use self::gpioa as gpioc;
361#[doc = "General purpose I/O"]
362pub type Gpiod = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
363impl core::fmt::Debug for Gpiod {
364 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
365 f.debug_struct("Gpiod").finish()
366 }
367}
368#[doc = "General purpose I/O"]
369pub use self::gpioa as gpiod;
370#[doc = "General purpose I/O"]
371pub type Gpioe = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
372impl core::fmt::Debug for Gpioe {
373 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
374 f.debug_struct("Gpioe").finish()
375 }
376}
377#[doc = "General purpose I/O"]
378pub use self::gpioa as gpioe;
379#[doc = "General purpose I/O"]
380pub type Gpiof = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
381impl core::fmt::Debug for Gpiof {
382 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
383 f.debug_struct("Gpiof").finish()
384 }
385}
386#[doc = "General purpose I/O"]
387pub use self::gpioa as gpiof;
388#[doc = "General purpose I/O"]
389pub type Gpiog = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
390impl core::fmt::Debug for Gpiog {
391 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
392 f.debug_struct("Gpiog").finish()
393 }
394}
395#[doc = "General purpose I/O"]
396pub use self::gpioa as gpiog;
397#[doc = "Alternate function I/O"]
398pub type Afio = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
399impl core::fmt::Debug for Afio {
400 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
401 f.debug_struct("Afio").finish()
402 }
403}
404#[doc = "Alternate function I/O"]
405pub mod afio;
406#[doc = "EXTI"]
407pub type Exti = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
408impl core::fmt::Debug for Exti {
409 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
410 f.debug_struct("Exti").finish()
411 }
412}
413#[doc = "EXTI"]
414pub mod exti;
415#[doc = "DMA controller"]
416pub type Dma1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
417impl core::fmt::Debug for Dma1 {
418 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
419 f.debug_struct("Dma1").finish()
420 }
421}
422#[doc = "DMA controller"]
423pub mod dma1;
424#[doc = "DMA controller"]
425pub type Dma2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
426impl core::fmt::Debug for Dma2 {
427 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
428 f.debug_struct("Dma2").finish()
429 }
430}
431#[doc = "DMA controller"]
432pub use self::dma1 as dma2;
433#[doc = "Secure digital input/output interface"]
434pub type Sdio = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
435impl core::fmt::Debug for Sdio {
436 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
437 f.debug_struct("Sdio").finish()
438 }
439}
440#[doc = "Secure digital input/output interface"]
441pub mod sdio;
442#[doc = "Real time clock"]
443pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
444impl core::fmt::Debug for Rtc {
445 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
446 f.debug_struct("Rtc").finish()
447 }
448}
449#[doc = "Real time clock"]
450pub mod rtc;
451#[doc = "Backup registers"]
452pub type Bkp = crate::Periph<bkp::RegisterBlock, 0x4000_6c00>;
453impl core::fmt::Debug for Bkp {
454 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
455 f.debug_struct("Bkp").finish()
456 }
457}
458#[doc = "Backup registers"]
459pub mod bkp;
460#[doc = "Independent watchdog"]
461pub type Iwdg = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
462impl core::fmt::Debug for Iwdg {
463 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
464 f.debug_struct("Iwdg").finish()
465 }
466}
467#[doc = "Independent watchdog"]
468pub mod iwdg;
469#[doc = "Window watchdog"]
470pub type Wwdg = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
471impl core::fmt::Debug for Wwdg {
472 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
473 f.debug_struct("Wwdg").finish()
474 }
475}
476#[doc = "Window watchdog"]
477pub mod wwdg;
478#[doc = "Advanced timer"]
479pub type Tim1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
480impl core::fmt::Debug for Tim1 {
481 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
482 f.debug_struct("Tim1").finish()
483 }
484}
485#[doc = "Advanced timer"]
486pub mod tim1;
487#[doc = "Advanced timer"]
488pub type Tim8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
489impl core::fmt::Debug for Tim8 {
490 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
491 f.debug_struct("Tim8").finish()
492 }
493}
494#[doc = "Advanced timer"]
495pub use self::tim1 as tim8;
496#[doc = "General purpose timer"]
497pub type Tim2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
498impl core::fmt::Debug for Tim2 {
499 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
500 f.debug_struct("Tim2").finish()
501 }
502}
503#[doc = "General purpose timer"]
504pub mod tim2;
505#[doc = "General purpose timer"]
506pub type Tim3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
507impl core::fmt::Debug for Tim3 {
508 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
509 f.debug_struct("Tim3").finish()
510 }
511}
512#[doc = "General purpose timer"]
513pub use self::tim2 as tim3;
514#[doc = "General purpose timer"]
515pub type Tim4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
516impl core::fmt::Debug for Tim4 {
517 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
518 f.debug_struct("Tim4").finish()
519 }
520}
521#[doc = "General purpose timer"]
522pub use self::tim2 as tim4;
523#[doc = "General purpose timer"]
524pub type Tim5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
525impl core::fmt::Debug for Tim5 {
526 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
527 f.debug_struct("Tim5").finish()
528 }
529}
530#[doc = "General purpose timer"]
531pub use self::tim2 as tim5;
532#[doc = "General purpose timer"]
533pub type Tim9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
534impl core::fmt::Debug for Tim9 {
535 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
536 f.debug_struct("Tim9").finish()
537 }
538}
539#[doc = "General purpose timer"]
540pub mod tim9;
541#[doc = "General purpose timer"]
542pub type Tim12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
543impl core::fmt::Debug for Tim12 {
544 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
545 f.debug_struct("Tim12").finish()
546 }
547}
548#[doc = "General purpose timer"]
549pub use self::tim9 as tim12;
550#[doc = "General purpose timer"]
551pub type Tim10 = crate::Periph<tim10::RegisterBlock, 0x4001_5000>;
552impl core::fmt::Debug for Tim10 {
553 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
554 f.debug_struct("Tim10").finish()
555 }
556}
557#[doc = "General purpose timer"]
558pub mod tim10;
559#[doc = "General purpose timer"]
560pub type Tim11 = crate::Periph<tim10::RegisterBlock, 0x4001_5400>;
561impl core::fmt::Debug for Tim11 {
562 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
563 f.debug_struct("Tim11").finish()
564 }
565}
566#[doc = "General purpose timer"]
567pub use self::tim10 as tim11;
568#[doc = "General purpose timer"]
569pub type Tim13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
570impl core::fmt::Debug for Tim13 {
571 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
572 f.debug_struct("Tim13").finish()
573 }
574}
575#[doc = "General purpose timer"]
576pub use self::tim10 as tim13;
577#[doc = "General purpose timer"]
578pub type Tim14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
579impl core::fmt::Debug for Tim14 {
580 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
581 f.debug_struct("Tim14").finish()
582 }
583}
584#[doc = "General purpose timer"]
585pub use self::tim10 as tim14;
586#[doc = "Basic timer"]
587pub type Tim6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
588impl core::fmt::Debug for Tim6 {
589 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
590 f.debug_struct("Tim6").finish()
591 }
592}
593#[doc = "Basic timer"]
594pub mod tim6;
595#[doc = "Basic timer"]
596pub type Tim7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
597impl core::fmt::Debug for Tim7 {
598 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
599 f.debug_struct("Tim7").finish()
600 }
601}
602#[doc = "Basic timer"]
603pub use self::tim6 as tim7;
604#[doc = "Inter integrated circuit"]
605pub type I2c1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
606impl core::fmt::Debug for I2c1 {
607 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
608 f.debug_struct("I2c1").finish()
609 }
610}
611#[doc = "Inter integrated circuit"]
612pub mod i2c1;
613#[doc = "Inter integrated circuit"]
614pub type I2c2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
615impl core::fmt::Debug for I2c2 {
616 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
617 f.debug_struct("I2c2").finish()
618 }
619}
620#[doc = "Inter integrated circuit"]
621pub use self::i2c1 as i2c2;
622#[doc = "Serial peripheral interface"]
623pub type Spi1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
624impl core::fmt::Debug for Spi1 {
625 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
626 f.debug_struct("Spi1").finish()
627 }
628}
629#[doc = "Serial peripheral interface"]
630pub mod spi1;
631#[doc = "Serial peripheral interface"]
632pub type Spi2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
633impl core::fmt::Debug for Spi2 {
634 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
635 f.debug_struct("Spi2").finish()
636 }
637}
638#[doc = "Serial peripheral interface"]
639pub use self::spi1 as spi2;
640#[doc = "Serial peripheral interface"]
641pub type Spi3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
642impl core::fmt::Debug for Spi3 {
643 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
644 f.debug_struct("Spi3").finish()
645 }
646}
647#[doc = "Serial peripheral interface"]
648pub use self::spi1 as spi3;
649#[doc = "Universal synchronous asynchronous receiver transmitter"]
650pub type Usart1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
651impl core::fmt::Debug for Usart1 {
652 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
653 f.debug_struct("Usart1").finish()
654 }
655}
656#[doc = "Universal synchronous asynchronous receiver transmitter"]
657pub mod usart1;
658#[doc = "Universal synchronous asynchronous receiver transmitter"]
659pub type Usart2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
660impl core::fmt::Debug for Usart2 {
661 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
662 f.debug_struct("Usart2").finish()
663 }
664}
665#[doc = "Universal synchronous asynchronous receiver transmitter"]
666pub use self::usart1 as usart2;
667#[doc = "Universal synchronous asynchronous receiver transmitter"]
668pub type Usart3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
669impl core::fmt::Debug for Usart3 {
670 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
671 f.debug_struct("Usart3").finish()
672 }
673}
674#[doc = "Universal synchronous asynchronous receiver transmitter"]
675pub use self::usart1 as usart3;
676#[doc = "Analog to digital converter"]
677pub type Adc1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
678impl core::fmt::Debug for Adc1 {
679 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
680 f.debug_struct("Adc1").finish()
681 }
682}
683#[doc = "Analog to digital converter"]
684pub mod adc1;
685#[doc = "Analog to digital converter"]
686pub type Adc2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
687impl core::fmt::Debug for Adc2 {
688 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
689 f.debug_struct("Adc2").finish()
690 }
691}
692#[doc = "Analog to digital converter"]
693pub mod adc2;
694#[doc = "Analog to digital converter"]
695pub type Adc3 = crate::Periph<adc2::RegisterBlock, 0x4001_3c00>;
696impl core::fmt::Debug for Adc3 {
697 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
698 f.debug_struct("Adc3").finish()
699 }
700}
701#[doc = "Analog to digital converter"]
702pub use self::adc2 as adc3;
703#[doc = "Controller area network"]
704pub type Can1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
705impl core::fmt::Debug for Can1 {
706 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
707 f.debug_struct("Can1").finish()
708 }
709}
710#[doc = "Controller area network"]
711pub mod can1;
712#[doc = "Controller area network"]
713pub type Can2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
714impl core::fmt::Debug for Can2 {
715 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
716 f.debug_struct("Can2").finish()
717 }
718}
719#[doc = "Controller area network"]
720pub use self::can1 as can2;
721#[doc = "Digital to analog converter"]
722pub type Dac = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
723impl core::fmt::Debug for Dac {
724 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
725 f.debug_struct("Dac").finish()
726 }
727}
728#[doc = "Digital to analog converter"]
729pub mod dac;
730#[doc = "Debug support"]
731pub type Dbg = crate::Periph<dbg::RegisterBlock, 0xe004_2000>;
732impl core::fmt::Debug for Dbg {
733 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
734 f.debug_struct("Dbg").finish()
735 }
736}
737#[doc = "Debug support"]
738pub mod dbg;
739#[doc = "Universal asynchronous receiver transmitter"]
740pub type Uart4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
741impl core::fmt::Debug for Uart4 {
742 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
743 f.debug_struct("Uart4").finish()
744 }
745}
746#[doc = "Universal asynchronous receiver transmitter"]
747pub mod uart4;
748#[doc = "Universal asynchronous receiver transmitter"]
749pub type Uart5 = crate::Periph<uart5::RegisterBlock, 0x4000_5000>;
750impl core::fmt::Debug for Uart5 {
751 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
752 f.debug_struct("Uart5").finish()
753 }
754}
755#[doc = "Universal asynchronous receiver transmitter"]
756pub mod uart5;
757#[doc = "CRC calculation unit"]
758pub type Crc = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
759impl core::fmt::Debug for Crc {
760 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
761 f.debug_struct("Crc").finish()
762 }
763}
764#[doc = "CRC calculation unit"]
765pub mod crc;
766#[doc = "FLASH"]
767pub type Flash = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
768impl core::fmt::Debug for Flash {
769 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
770 f.debug_struct("Flash").finish()
771 }
772}
773#[doc = "FLASH"]
774pub mod flash;
775#[doc = "Universal serial bus full-speed device interface"]
776pub type Usb = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
777impl core::fmt::Debug for Usb {
778 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
779 f.debug_struct("Usb").finish()
780 }
781}
782#[doc = "Universal serial bus full-speed device interface"]
783pub mod usb;
784#[doc = "USB on the go full speed"]
785pub type OtgFsDevice = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
786impl core::fmt::Debug for OtgFsDevice {
787 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
788 f.debug_struct("OtgFsDevice").finish()
789 }
790}
791#[doc = "USB on the go full speed"]
792pub mod otg_fs_device;
793#[doc = "USB on the go full speed"]
794pub type OtgFsGlobal = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
795impl core::fmt::Debug for OtgFsGlobal {
796 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
797 f.debug_struct("OtgFsGlobal").finish()
798 }
799}
800#[doc = "USB on the go full speed"]
801pub mod otg_fs_global;
802#[doc = "USB on the go full speed"]
803pub type OtgFsHost = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
804impl core::fmt::Debug for OtgFsHost {
805 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
806 f.debug_struct("OtgFsHost").finish()
807 }
808}
809#[doc = "USB on the go full speed"]
810pub mod otg_fs_host;
811#[doc = "USB on the go full speed"]
812pub type OtgFsPwrclk = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
813impl core::fmt::Debug for OtgFsPwrclk {
814 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
815 f.debug_struct("OtgFsPwrclk").finish()
816 }
817}
818#[doc = "USB on the go full speed"]
819pub mod otg_fs_pwrclk;
820#[doc = "Ethernet: MAC management counters"]
821pub type EthernetMmc = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
822impl core::fmt::Debug for EthernetMmc {
823 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824 f.debug_struct("EthernetMmc").finish()
825 }
826}
827#[doc = "Ethernet: MAC management counters"]
828pub mod ethernet_mmc;
829#[doc = "Ethernet: media access control"]
830pub type EthernetMac = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
831impl core::fmt::Debug for EthernetMac {
832 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
833 f.debug_struct("EthernetMac").finish()
834 }
835}
836#[doc = "Ethernet: media access control"]
837pub mod ethernet_mac;
838#[doc = "Ethernet: Precision time protocol"]
839pub type EthernetPtp = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
840impl core::fmt::Debug for EthernetPtp {
841 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
842 f.debug_struct("EthernetPtp").finish()
843 }
844}
845#[doc = "Ethernet: Precision time protocol"]
846pub mod ethernet_ptp;
847#[doc = "Ethernet: DMA controller operation"]
848pub type EthernetDma = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
849impl core::fmt::Debug for EthernetDma {
850 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
851 f.debug_struct("EthernetDma").finish()
852 }
853}
854#[doc = "Ethernet: DMA controller operation"]
855pub mod ethernet_dma;
856#[doc = "System control block ACTLR"]
857pub type ScbActrl = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
858impl core::fmt::Debug for ScbActrl {
859 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
860 f.debug_struct("ScbActrl").finish()
861 }
862}
863#[doc = "System control block ACTLR"]
864pub mod scb_actrl;
865#[doc = "Nested vectored interrupt controller"]
866pub type NvicStir = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
867impl core::fmt::Debug for NvicStir {
868 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
869 f.debug_struct("NvicStir").finish()
870 }
871}
872#[doc = "Nested vectored interrupt controller"]
873pub mod nvic_stir;
874#[doc = "SysTick timer"]
875pub type Stk = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
876impl core::fmt::Debug for Stk {
877 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
878 f.debug_struct("Stk").finish()
879 }
880}
881#[doc = "SysTick timer"]
882pub mod stk;
883#[unsafe(no_mangle)]
884static mut DEVICE_PERIPHERALS: bool = false;
885#[doc = r" All the peripherals."]
886#[allow(non_snake_case)]
887pub struct Peripherals {
888 #[doc = "FSMC"]
889 pub fsmc: Fsmc,
890 #[doc = "PWR"]
891 pub pwr: Pwr,
892 #[doc = "RCC"]
893 pub rcc: Rcc,
894 #[doc = "GPIOA"]
895 pub gpioa: Gpioa,
896 #[doc = "GPIOB"]
897 pub gpiob: Gpiob,
898 #[doc = "GPIOC"]
899 pub gpioc: Gpioc,
900 #[doc = "GPIOD"]
901 pub gpiod: Gpiod,
902 #[doc = "GPIOE"]
903 pub gpioe: Gpioe,
904 #[doc = "GPIOF"]
905 pub gpiof: Gpiof,
906 #[doc = "GPIOG"]
907 pub gpiog: Gpiog,
908 #[doc = "AFIO"]
909 pub afio: Afio,
910 #[doc = "EXTI"]
911 pub exti: Exti,
912 #[doc = "DMA1"]
913 pub dma1: Dma1,
914 #[doc = "DMA2"]
915 pub dma2: Dma2,
916 #[doc = "SDIO"]
917 pub sdio: Sdio,
918 #[doc = "RTC"]
919 pub rtc: Rtc,
920 #[doc = "BKP"]
921 pub bkp: Bkp,
922 #[doc = "IWDG"]
923 pub iwdg: Iwdg,
924 #[doc = "WWDG"]
925 pub wwdg: Wwdg,
926 #[doc = "TIM1"]
927 pub tim1: Tim1,
928 #[doc = "TIM8"]
929 pub tim8: Tim8,
930 #[doc = "TIM2"]
931 pub tim2: Tim2,
932 #[doc = "TIM3"]
933 pub tim3: Tim3,
934 #[doc = "TIM4"]
935 pub tim4: Tim4,
936 #[doc = "TIM5"]
937 pub tim5: Tim5,
938 #[doc = "TIM9"]
939 pub tim9: Tim9,
940 #[doc = "TIM12"]
941 pub tim12: Tim12,
942 #[doc = "TIM10"]
943 pub tim10: Tim10,
944 #[doc = "TIM11"]
945 pub tim11: Tim11,
946 #[doc = "TIM13"]
947 pub tim13: Tim13,
948 #[doc = "TIM14"]
949 pub tim14: Tim14,
950 #[doc = "TIM6"]
951 pub tim6: Tim6,
952 #[doc = "TIM7"]
953 pub tim7: Tim7,
954 #[doc = "I2C1"]
955 pub i2c1: I2c1,
956 #[doc = "I2C2"]
957 pub i2c2: I2c2,
958 #[doc = "SPI1"]
959 pub spi1: Spi1,
960 #[doc = "SPI2"]
961 pub spi2: Spi2,
962 #[doc = "SPI3"]
963 pub spi3: Spi3,
964 #[doc = "USART1"]
965 pub usart1: Usart1,
966 #[doc = "USART2"]
967 pub usart2: Usart2,
968 #[doc = "USART3"]
969 pub usart3: Usart3,
970 #[doc = "ADC1"]
971 pub adc1: Adc1,
972 #[doc = "ADC2"]
973 pub adc2: Adc2,
974 #[doc = "ADC3"]
975 pub adc3: Adc3,
976 #[doc = "CAN1"]
977 pub can1: Can1,
978 #[doc = "CAN2"]
979 pub can2: Can2,
980 #[doc = "DAC"]
981 pub dac: Dac,
982 #[doc = "DBG"]
983 pub dbg: Dbg,
984 #[doc = "UART4"]
985 pub uart4: Uart4,
986 #[doc = "UART5"]
987 pub uart5: Uart5,
988 #[doc = "CRC"]
989 pub crc: Crc,
990 #[doc = "FLASH"]
991 pub flash: Flash,
992 #[doc = "USB"]
993 pub usb: Usb,
994 #[doc = "OTG_FS_DEVICE"]
995 pub otg_fs_device: OtgFsDevice,
996 #[doc = "OTG_FS_GLOBAL"]
997 pub otg_fs_global: OtgFsGlobal,
998 #[doc = "OTG_FS_HOST"]
999 pub otg_fs_host: OtgFsHost,
1000 #[doc = "OTG_FS_PWRCLK"]
1001 pub otg_fs_pwrclk: OtgFsPwrclk,
1002 #[doc = "ETHERNET_MMC"]
1003 pub ethernet_mmc: EthernetMmc,
1004 #[doc = "ETHERNET_MAC"]
1005 pub ethernet_mac: EthernetMac,
1006 #[doc = "ETHERNET_PTP"]
1007 pub ethernet_ptp: EthernetPtp,
1008 #[doc = "ETHERNET_DMA"]
1009 pub ethernet_dma: EthernetDma,
1010 #[doc = "SCB_ACTRL"]
1011 pub scb_actrl: ScbActrl,
1012 #[doc = "NVIC_STIR"]
1013 pub nvic_stir: NvicStir,
1014 #[doc = "STK"]
1015 pub stk: Stk,
1016}
1017impl Peripherals {
1018 #[doc = r" Returns all the peripherals *once*."]
1019 #[cfg(feature = "critical-section")]
1020 #[inline]
1021 pub fn take() -> Option<Self> {
1022 critical_section::with(|_| {
1023 if unsafe { DEVICE_PERIPHERALS } {
1024 return None;
1025 }
1026 Some(unsafe { Peripherals::steal() })
1027 })
1028 }
1029 #[doc = r" Unchecked version of `Peripherals::take`."]
1030 #[doc = r""]
1031 #[doc = r" # Safety"]
1032 #[doc = r""]
1033 #[doc = r" Each of the returned peripherals must be used at most once."]
1034 #[inline]
1035 pub unsafe fn steal() -> Self {
1036 unsafe {
1037 DEVICE_PERIPHERALS = true;
1038 Peripherals {
1039 fsmc: Fsmc::steal(),
1040 pwr: Pwr::steal(),
1041 rcc: Rcc::steal(),
1042 gpioa: Gpioa::steal(),
1043 gpiob: Gpiob::steal(),
1044 gpioc: Gpioc::steal(),
1045 gpiod: Gpiod::steal(),
1046 gpioe: Gpioe::steal(),
1047 gpiof: Gpiof::steal(),
1048 gpiog: Gpiog::steal(),
1049 afio: Afio::steal(),
1050 exti: Exti::steal(),
1051 dma1: Dma1::steal(),
1052 dma2: Dma2::steal(),
1053 sdio: Sdio::steal(),
1054 rtc: Rtc::steal(),
1055 bkp: Bkp::steal(),
1056 iwdg: Iwdg::steal(),
1057 wwdg: Wwdg::steal(),
1058 tim1: Tim1::steal(),
1059 tim8: Tim8::steal(),
1060 tim2: Tim2::steal(),
1061 tim3: Tim3::steal(),
1062 tim4: Tim4::steal(),
1063 tim5: Tim5::steal(),
1064 tim9: Tim9::steal(),
1065 tim12: Tim12::steal(),
1066 tim10: Tim10::steal(),
1067 tim11: Tim11::steal(),
1068 tim13: Tim13::steal(),
1069 tim14: Tim14::steal(),
1070 tim6: Tim6::steal(),
1071 tim7: Tim7::steal(),
1072 i2c1: I2c1::steal(),
1073 i2c2: I2c2::steal(),
1074 spi1: Spi1::steal(),
1075 spi2: Spi2::steal(),
1076 spi3: Spi3::steal(),
1077 usart1: Usart1::steal(),
1078 usart2: Usart2::steal(),
1079 usart3: Usart3::steal(),
1080 adc1: Adc1::steal(),
1081 adc2: Adc2::steal(),
1082 adc3: Adc3::steal(),
1083 can1: Can1::steal(),
1084 can2: Can2::steal(),
1085 dac: Dac::steal(),
1086 dbg: Dbg::steal(),
1087 uart4: Uart4::steal(),
1088 uart5: Uart5::steal(),
1089 crc: Crc::steal(),
1090 flash: Flash::steal(),
1091 usb: Usb::steal(),
1092 otg_fs_device: OtgFsDevice::steal(),
1093 otg_fs_global: OtgFsGlobal::steal(),
1094 otg_fs_host: OtgFsHost::steal(),
1095 otg_fs_pwrclk: OtgFsPwrclk::steal(),
1096 ethernet_mmc: EthernetMmc::steal(),
1097 ethernet_mac: EthernetMac::steal(),
1098 ethernet_ptp: EthernetPtp::steal(),
1099 ethernet_dma: EthernetDma::steal(),
1100 scb_actrl: ScbActrl::steal(),
1101 nvic_stir: NvicStir::steal(),
1102 stk: Stk::steal(),
1103 }
1104 }
1105 }
1106}