stm32f1/stm32f107/tim6/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Master mode selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum MMS {
12    ///0: Use UG bit from TIMx_EGR register
13    Reset = 0,
14    ///1: Use CNT bit from TIMx_CEN register
15    Enable = 1,
16    ///2: Use the update event
17    Update = 2,
18}
19impl From<MMS> for u8 {
20    #[inline(always)]
21    fn from(variant: MMS) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for MMS {
26    type Ux = u8;
27}
28impl crate::IsEnum for MMS {}
29///Field `MMS` reader - Master mode selection
30pub type MMS_R = crate::FieldReader<MMS>;
31impl MMS_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<MMS> {
35        match self.bits {
36            0 => Some(MMS::Reset),
37            1 => Some(MMS::Enable),
38            2 => Some(MMS::Update),
39            _ => None,
40        }
41    }
42    ///Use UG bit from TIMx_EGR register
43    #[inline(always)]
44    pub fn is_reset(&self) -> bool {
45        *self == MMS::Reset
46    }
47    ///Use CNT bit from TIMx_CEN register
48    #[inline(always)]
49    pub fn is_enable(&self) -> bool {
50        *self == MMS::Enable
51    }
52    ///Use the update event
53    #[inline(always)]
54    pub fn is_update(&self) -> bool {
55        *self == MMS::Update
56    }
57}
58///Field `MMS` writer - Master mode selection
59pub type MMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MMS>;
60impl<'a, REG> MMS_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///Use UG bit from TIMx_EGR register
66    #[inline(always)]
67    pub fn reset(self) -> &'a mut crate::W<REG> {
68        self.variant(MMS::Reset)
69    }
70    ///Use CNT bit from TIMx_CEN register
71    #[inline(always)]
72    pub fn enable(self) -> &'a mut crate::W<REG> {
73        self.variant(MMS::Enable)
74    }
75    ///Use the update event
76    #[inline(always)]
77    pub fn update(self) -> &'a mut crate::W<REG> {
78        self.variant(MMS::Update)
79    }
80}
81impl R {
82    ///Bits 4:6 - Master mode selection
83    #[inline(always)]
84    pub fn mms(&self) -> MMS_R {
85        MMS_R::new(((self.bits >> 4) & 7) as u8)
86    }
87}
88impl core::fmt::Debug for R {
89    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
90        f.debug_struct("CR2").field("mms", &self.mms()).finish()
91    }
92}
93impl W {
94    ///Bits 4:6 - Master mode selection
95    #[inline(always)]
96    pub fn mms(&mut self) -> MMS_W<CR2rs> {
97        MMS_W::new(self, 4)
98    }
99}
100/**control register 2
101
102You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM6:CR2)*/
105pub struct CR2rs;
106impl crate::RegisterSpec for CR2rs {
107    type Ux = u32;
108}
109///`read()` method returns [`cr2::R`](R) reader structure
110impl crate::Readable for CR2rs {}
111///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
112impl crate::Writable for CR2rs {
113    type Safety = crate::Unsafe;
114}
115///`reset()` method sets CR2 to value 0
116impl crate::Resettable for CR2rs {}
stm32f1/stm32f107/tim6/cr2.rs

stm32f1/stm32f107/tim6/
cr2.rs
