stm32f1/stm32f107/tim2/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-4)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-4)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-4)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-4)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117impl R {
118    ///Capture/Compare (1-4) output enable
119    ///
120    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
121    #[inline(always)]
122    pub fn cce(&self, n: u8) -> CCE_R {
123        #[allow(clippy::no_effect)]
124        [(); 4][n as usize];
125        CCE_R::new(((self.bits >> (n * 4)) & 1) != 0)
126    }
127    ///Iterator for array of:
128    ///Capture/Compare (1-4) output enable
129    #[inline(always)]
130    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
131        (0..4).map(move |n| CCE_R::new(((self.bits >> (n * 4)) & 1) != 0))
132    }
133    ///Bit 0 - Capture/Compare 1 output enable
134    #[inline(always)]
135    pub fn cc1e(&self) -> CCE_R {
136        CCE_R::new((self.bits & 1) != 0)
137    }
138    ///Bit 4 - Capture/Compare 2 output enable
139    #[inline(always)]
140    pub fn cc2e(&self) -> CCE_R {
141        CCE_R::new(((self.bits >> 4) & 1) != 0)
142    }
143    ///Bit 8 - Capture/Compare 3 output enable
144    #[inline(always)]
145    pub fn cc3e(&self) -> CCE_R {
146        CCE_R::new(((self.bits >> 8) & 1) != 0)
147    }
148    ///Bit 12 - Capture/Compare 4 output enable
149    #[inline(always)]
150    pub fn cc4e(&self) -> CCE_R {
151        CCE_R::new(((self.bits >> 12) & 1) != 0)
152    }
153    ///Capture/Compare (1-4) output Polarity
154    ///
155    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
156    #[inline(always)]
157    pub fn ccp(&self, n: u8) -> CCP_R {
158        #[allow(clippy::no_effect)]
159        [(); 4][n as usize];
160        CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
161    }
162    ///Iterator for array of:
163    ///Capture/Compare (1-4) output Polarity
164    #[inline(always)]
165    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
166        (0..4).map(move |n| CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
167    }
168    ///Bit 1 - Capture/Compare 1 output Polarity
169    #[inline(always)]
170    pub fn cc1p(&self) -> CCP_R {
171        CCP_R::new(((self.bits >> 1) & 1) != 0)
172    }
173    ///Bit 5 - Capture/Compare 2 output Polarity
174    #[inline(always)]
175    pub fn cc2p(&self) -> CCP_R {
176        CCP_R::new(((self.bits >> 5) & 1) != 0)
177    }
178    ///Bit 9 - Capture/Compare 3 output Polarity
179    #[inline(always)]
180    pub fn cc3p(&self) -> CCP_R {
181        CCP_R::new(((self.bits >> 9) & 1) != 0)
182    }
183    ///Bit 13 - Capture/Compare 4 output Polarity
184    #[inline(always)]
185    pub fn cc4p(&self) -> CCP_R {
186        CCP_R::new(((self.bits >> 13) & 1) != 0)
187    }
188}
189impl core::fmt::Debug for R {
190    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
191        f.debug_struct("CCER")
192            .field("cc1p", &self.cc1p())
193            .field("cc2p", &self.cc2p())
194            .field("cc3p", &self.cc3p())
195            .field("cc4p", &self.cc4p())
196            .field("cc1e", &self.cc1e())
197            .field("cc2e", &self.cc2e())
198            .field("cc3e", &self.cc3e())
199            .field("cc4e", &self.cc4e())
200            .finish()
201    }
202}
203impl W {
204    ///Capture/Compare (1-4) output enable
205    ///
206    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
207    #[inline(always)]
208    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
209        #[allow(clippy::no_effect)]
210        [(); 4][n as usize];
211        CCE_W::new(self, n * 4)
212    }
213    ///Bit 0 - Capture/Compare 1 output enable
214    #[inline(always)]
215    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
216        CCE_W::new(self, 0)
217    }
218    ///Bit 4 - Capture/Compare 2 output enable
219    #[inline(always)]
220    pub fn cc2e(&mut self) -> CCE_W<CCERrs> {
221        CCE_W::new(self, 4)
222    }
223    ///Bit 8 - Capture/Compare 3 output enable
224    #[inline(always)]
225    pub fn cc3e(&mut self) -> CCE_W<CCERrs> {
226        CCE_W::new(self, 8)
227    }
228    ///Bit 12 - Capture/Compare 4 output enable
229    #[inline(always)]
230    pub fn cc4e(&mut self) -> CCE_W<CCERrs> {
231        CCE_W::new(self, 12)
232    }
233    ///Capture/Compare (1-4) output Polarity
234    ///
235    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
236    #[inline(always)]
237    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
238        #[allow(clippy::no_effect)]
239        [(); 4][n as usize];
240        CCP_W::new(self, n * 4 + 1)
241    }
242    ///Bit 1 - Capture/Compare 1 output Polarity
243    #[inline(always)]
244    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
245        CCP_W::new(self, 1)
246    }
247    ///Bit 5 - Capture/Compare 2 output Polarity
248    #[inline(always)]
249    pub fn cc2p(&mut self) -> CCP_W<CCERrs> {
250        CCP_W::new(self, 5)
251    }
252    ///Bit 9 - Capture/Compare 3 output Polarity
253    #[inline(always)]
254    pub fn cc3p(&mut self) -> CCP_W<CCERrs> {
255        CCP_W::new(self, 9)
256    }
257    ///Bit 13 - Capture/Compare 4 output Polarity
258    #[inline(always)]
259    pub fn cc4p(&mut self) -> CCP_W<CCERrs> {
260        CCP_W::new(self, 13)
261    }
262}
263/**capture/compare enable register
264
265You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
266
267See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2:CCER)*/
268pub struct CCERrs;
269impl crate::RegisterSpec for CCERrs {
270    type Ux = u32;
271}
272///`read()` method returns [`ccer::R`](R) reader structure
273impl crate::Readable for CCERrs {}
274///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
275impl crate::Writable for CCERrs {
276    type Safety = crate::Unsafe;
277}
278///`reset()` method sets CCER to value 0
279impl crate::Resettable for CCERrs {}
stm32f1/stm32f107/tim2/ccer.rs

stm32f1/stm32f107/tim2/
ccer.rs
