stm32f1/stm32f107/tim13/
ccmr1_input.rs

1///Register `CCMR1_Input` reader
2pub type R = crate::R<CCMR1_INPUTrs>;
3///Register `CCMR1_Input` writer
4pub type W = crate::W<CCMR1_INPUTrs>;
5/**Capture/Compare 1 selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum CC1S {
12    ///1: CC1 channel is configured as input, IC1 is mapped on TI1
13    Ti1 = 1,
14}
15impl From<CC1S> for u8 {
16    #[inline(always)]
17    fn from(variant: CC1S) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for CC1S {
22    type Ux = u8;
23}
24impl crate::IsEnum for CC1S {}
25///Field `CC1S` reader - Capture/Compare 1 selection
26pub type CC1S_R = crate::FieldReader<CC1S>;
27impl CC1S_R {
28    ///Get enumerated values variant
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<CC1S> {
31        match self.bits {
32            1 => Some(CC1S::Ti1),
33            _ => None,
34        }
35    }
36    ///CC1 channel is configured as input, IC1 is mapped on TI1
37    #[inline(always)]
38    pub fn is_ti1(&self) -> bool {
39        *self == CC1S::Ti1
40    }
41}
42///Field `CC1S` writer - Capture/Compare 1 selection
43pub type CC1S_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC1S>;
44impl<'a, REG> CC1S_W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47    REG::Ux: From<u8>,
48{
49    ///CC1 channel is configured as input, IC1 is mapped on TI1
50    #[inline(always)]
51    pub fn ti1(self) -> &'a mut crate::W<REG> {
52        self.variant(CC1S::Ti1)
53    }
54}
55/**Input capture %s prescaler
56
57Value on reset: 0*/
58#[cfg_attr(feature = "defmt", derive(defmt::Format))]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60#[repr(u8)]
61pub enum ICPRESCALER {
62    ///0: No prescaler, capture is done each time an edge is detected on the capture input
63    NoPrescaler = 0,
64    ///1: Capture is done once every 2 events
65    TwoEvents = 1,
66    ///2: Capture is done once every 4 events
67    FourEvents = 2,
68    ///3: Capture is done once every 8 events
69    EightEvents = 3,
70}
71impl From<ICPRESCALER> for u8 {
72    #[inline(always)]
73    fn from(variant: ICPRESCALER) -> Self {
74        variant as _
75    }
76}
77impl crate::FieldSpec for ICPRESCALER {
78    type Ux = u8;
79}
80impl crate::IsEnum for ICPRESCALER {}
81///Field `ICPSC(1-1)` reader - Input capture %s prescaler
82pub type ICPSC_R = crate::FieldReader<ICPRESCALER>;
83impl ICPSC_R {
84    ///Get enumerated values variant
85    #[inline(always)]
86    pub const fn variant(&self) -> ICPRESCALER {
87        match self.bits {
88            0 => ICPRESCALER::NoPrescaler,
89            1 => ICPRESCALER::TwoEvents,
90            2 => ICPRESCALER::FourEvents,
91            3 => ICPRESCALER::EightEvents,
92            _ => unreachable!(),
93        }
94    }
95    ///No prescaler, capture is done each time an edge is detected on the capture input
96    #[inline(always)]
97    pub fn is_no_prescaler(&self) -> bool {
98        *self == ICPRESCALER::NoPrescaler
99    }
100    ///Capture is done once every 2 events
101    #[inline(always)]
102    pub fn is_two_events(&self) -> bool {
103        *self == ICPRESCALER::TwoEvents
104    }
105    ///Capture is done once every 4 events
106    #[inline(always)]
107    pub fn is_four_events(&self) -> bool {
108        *self == ICPRESCALER::FourEvents
109    }
110    ///Capture is done once every 8 events
111    #[inline(always)]
112    pub fn is_eight_events(&self) -> bool {
113        *self == ICPRESCALER::EightEvents
114    }
115}
116///Field `ICPSC(1-1)` writer - Input capture %s prescaler
117pub type ICPSC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ICPRESCALER, crate::Safe>;
118impl<'a, REG> ICPSC_W<'a, REG>
119where
120    REG: crate::Writable + crate::RegisterSpec,
121    REG::Ux: From<u8>,
122{
123    ///No prescaler, capture is done each time an edge is detected on the capture input
124    #[inline(always)]
125    pub fn no_prescaler(self) -> &'a mut crate::W<REG> {
126        self.variant(ICPRESCALER::NoPrescaler)
127    }
128    ///Capture is done once every 2 events
129    #[inline(always)]
130    pub fn two_events(self) -> &'a mut crate::W<REG> {
131        self.variant(ICPRESCALER::TwoEvents)
132    }
133    ///Capture is done once every 4 events
134    #[inline(always)]
135    pub fn four_events(self) -> &'a mut crate::W<REG> {
136        self.variant(ICPRESCALER::FourEvents)
137    }
138    ///Capture is done once every 8 events
139    #[inline(always)]
140    pub fn eight_events(self) -> &'a mut crate::W<REG> {
141        self.variant(ICPRESCALER::EightEvents)
142    }
143}
144/**Input capture %s filter
145
146Value on reset: 0*/
147#[cfg_attr(feature = "defmt", derive(defmt::Format))]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149#[repr(u8)]
150pub enum ICFILTER {
151    ///0: No filter, sampling is done at fDTS
152    NoFilter = 0,
153    ///1: fSAMPLING=fCK_INT, N=2
154    FckIntN2 = 1,
155    ///2: fSAMPLING=fCK_INT, N=4
156    FckIntN4 = 2,
157    ///3: fSAMPLING=fCK_INT, N=8
158    FckIntN8 = 3,
159    ///4: fSAMPLING=fDTS/2, N=6
160    FdtsDiv2N6 = 4,
161    ///5: fSAMPLING=fDTS/2, N=8
162    FdtsDiv2N8 = 5,
163    ///6: fSAMPLING=fDTS/4, N=6
164    FdtsDiv4N6 = 6,
165    ///7: fSAMPLING=fDTS/4, N=8
166    FdtsDiv4N8 = 7,
167    ///8: fSAMPLING=fDTS/8, N=6
168    FdtsDiv8N6 = 8,
169    ///9: fSAMPLING=fDTS/8, N=8
170    FdtsDiv8N8 = 9,
171    ///10: fSAMPLING=fDTS/16, N=5
172    FdtsDiv16N5 = 10,
173    ///11: fSAMPLING=fDTS/16, N=6
174    FdtsDiv16N6 = 11,
175    ///12: fSAMPLING=fDTS/16, N=8
176    FdtsDiv16N8 = 12,
177    ///13: fSAMPLING=fDTS/32, N=5
178    FdtsDiv32N5 = 13,
179    ///14: fSAMPLING=fDTS/32, N=6
180    FdtsDiv32N6 = 14,
181    ///15: fSAMPLING=fDTS/32, N=8
182    FdtsDiv32N8 = 15,
183}
184impl From<ICFILTER> for u8 {
185    #[inline(always)]
186    fn from(variant: ICFILTER) -> Self {
187        variant as _
188    }
189}
190impl crate::FieldSpec for ICFILTER {
191    type Ux = u8;
192}
193impl crate::IsEnum for ICFILTER {}
194///Field `ICF(1-1)` reader - Input capture %s filter
195pub type ICF_R = crate::FieldReader<ICFILTER>;
196impl ICF_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> ICFILTER {
200        match self.bits {
201            0 => ICFILTER::NoFilter,
202            1 => ICFILTER::FckIntN2,
203            2 => ICFILTER::FckIntN4,
204            3 => ICFILTER::FckIntN8,
205            4 => ICFILTER::FdtsDiv2N6,
206            5 => ICFILTER::FdtsDiv2N8,
207            6 => ICFILTER::FdtsDiv4N6,
208            7 => ICFILTER::FdtsDiv4N8,
209            8 => ICFILTER::FdtsDiv8N6,
210            9 => ICFILTER::FdtsDiv8N8,
211            10 => ICFILTER::FdtsDiv16N5,
212            11 => ICFILTER::FdtsDiv16N6,
213            12 => ICFILTER::FdtsDiv16N8,
214            13 => ICFILTER::FdtsDiv32N5,
215            14 => ICFILTER::FdtsDiv32N6,
216            15 => ICFILTER::FdtsDiv32N8,
217            _ => unreachable!(),
218        }
219    }
220    ///No filter, sampling is done at fDTS
221    #[inline(always)]
222    pub fn is_no_filter(&self) -> bool {
223        *self == ICFILTER::NoFilter
224    }
225    ///fSAMPLING=fCK_INT, N=2
226    #[inline(always)]
227    pub fn is_fck_int_n2(&self) -> bool {
228        *self == ICFILTER::FckIntN2
229    }
230    ///fSAMPLING=fCK_INT, N=4
231    #[inline(always)]
232    pub fn is_fck_int_n4(&self) -> bool {
233        *self == ICFILTER::FckIntN4
234    }
235    ///fSAMPLING=fCK_INT, N=8
236    #[inline(always)]
237    pub fn is_fck_int_n8(&self) -> bool {
238        *self == ICFILTER::FckIntN8
239    }
240    ///fSAMPLING=fDTS/2, N=6
241    #[inline(always)]
242    pub fn is_fdts_div2_n6(&self) -> bool {
243        *self == ICFILTER::FdtsDiv2N6
244    }
245    ///fSAMPLING=fDTS/2, N=8
246    #[inline(always)]
247    pub fn is_fdts_div2_n8(&self) -> bool {
248        *self == ICFILTER::FdtsDiv2N8
249    }
250    ///fSAMPLING=fDTS/4, N=6
251    #[inline(always)]
252    pub fn is_fdts_div4_n6(&self) -> bool {
253        *self == ICFILTER::FdtsDiv4N6
254    }
255    ///fSAMPLING=fDTS/4, N=8
256    #[inline(always)]
257    pub fn is_fdts_div4_n8(&self) -> bool {
258        *self == ICFILTER::FdtsDiv4N8
259    }
260    ///fSAMPLING=fDTS/8, N=6
261    #[inline(always)]
262    pub fn is_fdts_div8_n6(&self) -> bool {
263        *self == ICFILTER::FdtsDiv8N6
264    }
265    ///fSAMPLING=fDTS/8, N=8
266    #[inline(always)]
267    pub fn is_fdts_div8_n8(&self) -> bool {
268        *self == ICFILTER::FdtsDiv8N8
269    }
270    ///fSAMPLING=fDTS/16, N=5
271    #[inline(always)]
272    pub fn is_fdts_div16_n5(&self) -> bool {
273        *self == ICFILTER::FdtsDiv16N5
274    }
275    ///fSAMPLING=fDTS/16, N=6
276    #[inline(always)]
277    pub fn is_fdts_div16_n6(&self) -> bool {
278        *self == ICFILTER::FdtsDiv16N6
279    }
280    ///fSAMPLING=fDTS/16, N=8
281    #[inline(always)]
282    pub fn is_fdts_div16_n8(&self) -> bool {
283        *self == ICFILTER::FdtsDiv16N8
284    }
285    ///fSAMPLING=fDTS/32, N=5
286    #[inline(always)]
287    pub fn is_fdts_div32_n5(&self) -> bool {
288        *self == ICFILTER::FdtsDiv32N5
289    }
290    ///fSAMPLING=fDTS/32, N=6
291    #[inline(always)]
292    pub fn is_fdts_div32_n6(&self) -> bool {
293        *self == ICFILTER::FdtsDiv32N6
294    }
295    ///fSAMPLING=fDTS/32, N=8
296    #[inline(always)]
297    pub fn is_fdts_div32_n8(&self) -> bool {
298        *self == ICFILTER::FdtsDiv32N8
299    }
300}
301///Field `ICF(1-1)` writer - Input capture %s filter
302pub type ICF_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ICFILTER, crate::Safe>;
303impl<'a, REG> ICF_W<'a, REG>
304where
305    REG: crate::Writable + crate::RegisterSpec,
306    REG::Ux: From<u8>,
307{
308    ///No filter, sampling is done at fDTS
309    #[inline(always)]
310    pub fn no_filter(self) -> &'a mut crate::W<REG> {
311        self.variant(ICFILTER::NoFilter)
312    }
313    ///fSAMPLING=fCK_INT, N=2
314    #[inline(always)]
315    pub fn fck_int_n2(self) -> &'a mut crate::W<REG> {
316        self.variant(ICFILTER::FckIntN2)
317    }
318    ///fSAMPLING=fCK_INT, N=4
319    #[inline(always)]
320    pub fn fck_int_n4(self) -> &'a mut crate::W<REG> {
321        self.variant(ICFILTER::FckIntN4)
322    }
323    ///fSAMPLING=fCK_INT, N=8
324    #[inline(always)]
325    pub fn fck_int_n8(self) -> &'a mut crate::W<REG> {
326        self.variant(ICFILTER::FckIntN8)
327    }
328    ///fSAMPLING=fDTS/2, N=6
329    #[inline(always)]
330    pub fn fdts_div2_n6(self) -> &'a mut crate::W<REG> {
331        self.variant(ICFILTER::FdtsDiv2N6)
332    }
333    ///fSAMPLING=fDTS/2, N=8
334    #[inline(always)]
335    pub fn fdts_div2_n8(self) -> &'a mut crate::W<REG> {
336        self.variant(ICFILTER::FdtsDiv2N8)
337    }
338    ///fSAMPLING=fDTS/4, N=6
339    #[inline(always)]
340    pub fn fdts_div4_n6(self) -> &'a mut crate::W<REG> {
341        self.variant(ICFILTER::FdtsDiv4N6)
342    }
343    ///fSAMPLING=fDTS/4, N=8
344    #[inline(always)]
345    pub fn fdts_div4_n8(self) -> &'a mut crate::W<REG> {
346        self.variant(ICFILTER::FdtsDiv4N8)
347    }
348    ///fSAMPLING=fDTS/8, N=6
349    #[inline(always)]
350    pub fn fdts_div8_n6(self) -> &'a mut crate::W<REG> {
351        self.variant(ICFILTER::FdtsDiv8N6)
352    }
353    ///fSAMPLING=fDTS/8, N=8
354    #[inline(always)]
355    pub fn fdts_div8_n8(self) -> &'a mut crate::W<REG> {
356        self.variant(ICFILTER::FdtsDiv8N8)
357    }
358    ///fSAMPLING=fDTS/16, N=5
359    #[inline(always)]
360    pub fn fdts_div16_n5(self) -> &'a mut crate::W<REG> {
361        self.variant(ICFILTER::FdtsDiv16N5)
362    }
363    ///fSAMPLING=fDTS/16, N=6
364    #[inline(always)]
365    pub fn fdts_div16_n6(self) -> &'a mut crate::W<REG> {
366        self.variant(ICFILTER::FdtsDiv16N6)
367    }
368    ///fSAMPLING=fDTS/16, N=8
369    #[inline(always)]
370    pub fn fdts_div16_n8(self) -> &'a mut crate::W<REG> {
371        self.variant(ICFILTER::FdtsDiv16N8)
372    }
373    ///fSAMPLING=fDTS/32, N=5
374    #[inline(always)]
375    pub fn fdts_div32_n5(self) -> &'a mut crate::W<REG> {
376        self.variant(ICFILTER::FdtsDiv32N5)
377    }
378    ///fSAMPLING=fDTS/32, N=6
379    #[inline(always)]
380    pub fn fdts_div32_n6(self) -> &'a mut crate::W<REG> {
381        self.variant(ICFILTER::FdtsDiv32N6)
382    }
383    ///fSAMPLING=fDTS/32, N=8
384    #[inline(always)]
385    pub fn fdts_div32_n8(self) -> &'a mut crate::W<REG> {
386        self.variant(ICFILTER::FdtsDiv32N8)
387    }
388}
389impl R {
390    ///Bits 0:1 - Capture/Compare 1 selection
391    #[inline(always)]
392    pub fn cc1s(&self) -> CC1S_R {
393        CC1S_R::new((self.bits & 3) as u8)
394    }
395    ///Input capture (1-1) prescaler
396    ///
397    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1PSC` field.</div>
398    #[inline(always)]
399    pub fn icpsc(&self, n: u8) -> ICPSC_R {
400        #[allow(clippy::no_effect)]
401        [(); 1][n as usize];
402        ICPSC_R::new(((self.bits >> (n * 0 + 2)) & 3) as u8)
403    }
404    ///Iterator for array of:
405    ///Input capture (1-1) prescaler
406    #[inline(always)]
407    pub fn icpsc_iter(&self) -> impl Iterator<Item = ICPSC_R> + '_ {
408        (0..1).map(move |n| ICPSC_R::new(((self.bits >> (n * 0 + 2)) & 3) as u8))
409    }
410    ///Bits 2:3 - Input capture 1 prescaler
411    #[inline(always)]
412    pub fn ic1psc(&self) -> ICPSC_R {
413        ICPSC_R::new(((self.bits >> 2) & 3) as u8)
414    }
415    ///Input capture (1-1) filter
416    ///
417    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1F` field.</div>
418    #[inline(always)]
419    pub fn icf(&self, n: u8) -> ICF_R {
420        #[allow(clippy::no_effect)]
421        [(); 1][n as usize];
422        ICF_R::new(((self.bits >> (n * 0 + 4)) & 0x0f) as u8)
423    }
424    ///Iterator for array of:
425    ///Input capture (1-1) filter
426    #[inline(always)]
427    pub fn icf_iter(&self) -> impl Iterator<Item = ICF_R> + '_ {
428        (0..1).map(move |n| ICF_R::new(((self.bits >> (n * 0 + 4)) & 0x0f) as u8))
429    }
430    ///Bits 4:7 - Input capture 1 filter
431    #[inline(always)]
432    pub fn ic1f(&self) -> ICF_R {
433        ICF_R::new(((self.bits >> 4) & 0x0f) as u8)
434    }
435}
436impl core::fmt::Debug for R {
437    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
438        f.debug_struct("CCMR1_Input")
439            .field("ic1f", &self.ic1f())
440            .field("ic1psc", &self.ic1psc())
441            .field("cc1s", &self.cc1s())
442            .finish()
443    }
444}
445impl W {
446    ///Bits 0:1 - Capture/Compare 1 selection
447    #[inline(always)]
448    pub fn cc1s(&mut self) -> CC1S_W<CCMR1_INPUTrs> {
449        CC1S_W::new(self, 0)
450    }
451    ///Input capture (1-1) prescaler
452    ///
453    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1PSC` field.</div>
454    #[inline(always)]
455    pub fn icpsc(&mut self, n: u8) -> ICPSC_W<CCMR1_INPUTrs> {
456        #[allow(clippy::no_effect)]
457        [(); 1][n as usize];
458        ICPSC_W::new(self, n * 0 + 2)
459    }
460    ///Bits 2:3 - Input capture 1 prescaler
461    #[inline(always)]
462    pub fn ic1psc(&mut self) -> ICPSC_W<CCMR1_INPUTrs> {
463        ICPSC_W::new(self, 2)
464    }
465    ///Input capture (1-1) filter
466    ///
467    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1F` field.</div>
468    #[inline(always)]
469    pub fn icf(&mut self, n: u8) -> ICF_W<CCMR1_INPUTrs> {
470        #[allow(clippy::no_effect)]
471        [(); 1][n as usize];
472        ICF_W::new(self, n * 0 + 4)
473    }
474    ///Bits 4:7 - Input capture 1 filter
475    #[inline(always)]
476    pub fn ic1f(&mut self) -> ICF_W<CCMR1_INPUTrs> {
477        ICF_W::new(self, 4)
478    }
479}
480/**capture/compare mode register (input mode)
481
482You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
483
484See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13:CCMR1_Input)*/
485pub struct CCMR1_INPUTrs;
486impl crate::RegisterSpec for CCMR1_INPUTrs {
487    type Ux = u32;
488}
489///`read()` method returns [`ccmr1_input::R`](R) reader structure
490impl crate::Readable for CCMR1_INPUTrs {}
491///`write(|w| ..)` method takes [`ccmr1_input::W`](W) writer structure
492impl crate::Writable for CCMR1_INPUTrs {
493    type Safety = crate::Unsafe;
494}
495///`reset()` method sets CCMR1_Input to value 0
496impl crate::Resettable for CCMR1_INPUTrs {}
stm32f1/stm32f107/tim13/ccmr1_input.rs

stm32f1/stm32f107/tim13/
ccmr1_input.rs
