stm32f1/stm32f107/spi1/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Rx buffer DMA enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RXDMAEN {
11    ///0: Rx buffer DMA disabled
12    Disabled = 0,
13    ///1: Rx buffer DMA enabled
14    Enabled = 1,
15}
16impl From<RXDMAEN> for bool {
17    #[inline(always)]
18    fn from(variant: RXDMAEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `RXDMAEN` reader - Rx buffer DMA enable
23pub type RXDMAEN_R = crate::BitReader<RXDMAEN>;
24impl RXDMAEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RXDMAEN {
28        match self.bits {
29            false => RXDMAEN::Disabled,
30            true => RXDMAEN::Enabled,
31        }
32    }
33    ///Rx buffer DMA disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == RXDMAEN::Disabled
37    }
38    ///Rx buffer DMA enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == RXDMAEN::Enabled
42    }
43}
44///Field `RXDMAEN` writer - Rx buffer DMA enable
45pub type RXDMAEN_W<'a, REG> = crate::BitWriter<'a, REG, RXDMAEN>;
46impl<'a, REG> RXDMAEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Rx buffer DMA disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(RXDMAEN::Disabled)
54    }
55    ///Rx buffer DMA enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(RXDMAEN::Enabled)
59    }
60}
61/**Tx buffer DMA enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum TXDMAEN {
67    ///0: Tx buffer DMA disabled
68    Disabled = 0,
69    ///1: Tx buffer DMA enabled
70    Enabled = 1,
71}
72impl From<TXDMAEN> for bool {
73    #[inline(always)]
74    fn from(variant: TXDMAEN) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `TXDMAEN` reader - Tx buffer DMA enable
79pub type TXDMAEN_R = crate::BitReader<TXDMAEN>;
80impl TXDMAEN_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> TXDMAEN {
84        match self.bits {
85            false => TXDMAEN::Disabled,
86            true => TXDMAEN::Enabled,
87        }
88    }
89    ///Tx buffer DMA disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == TXDMAEN::Disabled
93    }
94    ///Tx buffer DMA enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == TXDMAEN::Enabled
98    }
99}
100///Field `TXDMAEN` writer - Tx buffer DMA enable
101pub type TXDMAEN_W<'a, REG> = crate::BitWriter<'a, REG, TXDMAEN>;
102impl<'a, REG> TXDMAEN_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Tx buffer DMA disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(TXDMAEN::Disabled)
110    }
111    ///Tx buffer DMA enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(TXDMAEN::Enabled)
115    }
116}
117/**SS output enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum SSOE {
123    ///0: SS output is disabled in master mode
124    Disabled = 0,
125    ///1: SS output is enabled in master mode
126    Enabled = 1,
127}
128impl From<SSOE> for bool {
129    #[inline(always)]
130    fn from(variant: SSOE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `SSOE` reader - SS output enable
135pub type SSOE_R = crate::BitReader<SSOE>;
136impl SSOE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> SSOE {
140        match self.bits {
141            false => SSOE::Disabled,
142            true => SSOE::Enabled,
143        }
144    }
145    ///SS output is disabled in master mode
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == SSOE::Disabled
149    }
150    ///SS output is enabled in master mode
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == SSOE::Enabled
154    }
155}
156///Field `SSOE` writer - SS output enable
157pub type SSOE_W<'a, REG> = crate::BitWriter<'a, REG, SSOE>;
158impl<'a, REG> SSOE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///SS output is disabled in master mode
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(SSOE::Disabled)
166    }
167    ///SS output is enabled in master mode
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(SSOE::Enabled)
171    }
172}
173/**Error interrupt enable
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum ERRIE {
179    ///0: Error interrupt masked
180    Masked = 0,
181    ///1: Error interrupt not masked
182    NotMasked = 1,
183}
184impl From<ERRIE> for bool {
185    #[inline(always)]
186    fn from(variant: ERRIE) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `ERRIE` reader - Error interrupt enable
191pub type ERRIE_R = crate::BitReader<ERRIE>;
192impl ERRIE_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> ERRIE {
196        match self.bits {
197            false => ERRIE::Masked,
198            true => ERRIE::NotMasked,
199        }
200    }
201    ///Error interrupt masked
202    #[inline(always)]
203    pub fn is_masked(&self) -> bool {
204        *self == ERRIE::Masked
205    }
206    ///Error interrupt not masked
207    #[inline(always)]
208    pub fn is_not_masked(&self) -> bool {
209        *self == ERRIE::NotMasked
210    }
211}
212///Field `ERRIE` writer - Error interrupt enable
213pub type ERRIE_W<'a, REG> = crate::BitWriter<'a, REG, ERRIE>;
214impl<'a, REG> ERRIE_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Error interrupt masked
219    #[inline(always)]
220    pub fn masked(self) -> &'a mut crate::W<REG> {
221        self.variant(ERRIE::Masked)
222    }
223    ///Error interrupt not masked
224    #[inline(always)]
225    pub fn not_masked(self) -> &'a mut crate::W<REG> {
226        self.variant(ERRIE::NotMasked)
227    }
228}
229/**RX buffer not empty interrupt enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum RXNEIE {
235    ///0: RXE interrupt masked
236    Masked = 0,
237    ///1: RXE interrupt not masked
238    NotMasked = 1,
239}
240impl From<RXNEIE> for bool {
241    #[inline(always)]
242    fn from(variant: RXNEIE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `RXNEIE` reader - RX buffer not empty interrupt enable
247pub type RXNEIE_R = crate::BitReader<RXNEIE>;
248impl RXNEIE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> RXNEIE {
252        match self.bits {
253            false => RXNEIE::Masked,
254            true => RXNEIE::NotMasked,
255        }
256    }
257    ///RXE interrupt masked
258    #[inline(always)]
259    pub fn is_masked(&self) -> bool {
260        *self == RXNEIE::Masked
261    }
262    ///RXE interrupt not masked
263    #[inline(always)]
264    pub fn is_not_masked(&self) -> bool {
265        *self == RXNEIE::NotMasked
266    }
267}
268///Field `RXNEIE` writer - RX buffer not empty interrupt enable
269pub type RXNEIE_W<'a, REG> = crate::BitWriter<'a, REG, RXNEIE>;
270impl<'a, REG> RXNEIE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///RXE interrupt masked
275    #[inline(always)]
276    pub fn masked(self) -> &'a mut crate::W<REG> {
277        self.variant(RXNEIE::Masked)
278    }
279    ///RXE interrupt not masked
280    #[inline(always)]
281    pub fn not_masked(self) -> &'a mut crate::W<REG> {
282        self.variant(RXNEIE::NotMasked)
283    }
284}
285/**Tx buffer empty interrupt enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum TXEIE {
291    ///0: TXE interrupt masked
292    Masked = 0,
293    ///1: TXE interrupt not masked
294    NotMasked = 1,
295}
296impl From<TXEIE> for bool {
297    #[inline(always)]
298    fn from(variant: TXEIE) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `TXEIE` reader - Tx buffer empty interrupt enable
303pub type TXEIE_R = crate::BitReader<TXEIE>;
304impl TXEIE_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> TXEIE {
308        match self.bits {
309            false => TXEIE::Masked,
310            true => TXEIE::NotMasked,
311        }
312    }
313    ///TXE interrupt masked
314    #[inline(always)]
315    pub fn is_masked(&self) -> bool {
316        *self == TXEIE::Masked
317    }
318    ///TXE interrupt not masked
319    #[inline(always)]
320    pub fn is_not_masked(&self) -> bool {
321        *self == TXEIE::NotMasked
322    }
323}
324///Field `TXEIE` writer - Tx buffer empty interrupt enable
325pub type TXEIE_W<'a, REG> = crate::BitWriter<'a, REG, TXEIE>;
326impl<'a, REG> TXEIE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///TXE interrupt masked
331    #[inline(always)]
332    pub fn masked(self) -> &'a mut crate::W<REG> {
333        self.variant(TXEIE::Masked)
334    }
335    ///TXE interrupt not masked
336    #[inline(always)]
337    pub fn not_masked(self) -> &'a mut crate::W<REG> {
338        self.variant(TXEIE::NotMasked)
339    }
340}
341impl R {
342    ///Bit 0 - Rx buffer DMA enable
343    #[inline(always)]
344    pub fn rxdmaen(&self) -> RXDMAEN_R {
345        RXDMAEN_R::new((self.bits & 1) != 0)
346    }
347    ///Bit 1 - Tx buffer DMA enable
348    #[inline(always)]
349    pub fn txdmaen(&self) -> TXDMAEN_R {
350        TXDMAEN_R::new(((self.bits >> 1) & 1) != 0)
351    }
352    ///Bit 2 - SS output enable
353    #[inline(always)]
354    pub fn ssoe(&self) -> SSOE_R {
355        SSOE_R::new(((self.bits >> 2) & 1) != 0)
356    }
357    ///Bit 5 - Error interrupt enable
358    #[inline(always)]
359    pub fn errie(&self) -> ERRIE_R {
360        ERRIE_R::new(((self.bits >> 5) & 1) != 0)
361    }
362    ///Bit 6 - RX buffer not empty interrupt enable
363    #[inline(always)]
364    pub fn rxneie(&self) -> RXNEIE_R {
365        RXNEIE_R::new(((self.bits >> 6) & 1) != 0)
366    }
367    ///Bit 7 - Tx buffer empty interrupt enable
368    #[inline(always)]
369    pub fn txeie(&self) -> TXEIE_R {
370        TXEIE_R::new(((self.bits >> 7) & 1) != 0)
371    }
372}
373impl core::fmt::Debug for R {
374    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
375        f.debug_struct("CR2")
376            .field("txeie", &self.txeie())
377            .field("rxneie", &self.rxneie())
378            .field("errie", &self.errie())
379            .field("ssoe", &self.ssoe())
380            .field("txdmaen", &self.txdmaen())
381            .field("rxdmaen", &self.rxdmaen())
382            .finish()
383    }
384}
385impl W {
386    ///Bit 0 - Rx buffer DMA enable
387    #[inline(always)]
388    pub fn rxdmaen(&mut self) -> RXDMAEN_W<CR2rs> {
389        RXDMAEN_W::new(self, 0)
390    }
391    ///Bit 1 - Tx buffer DMA enable
392    #[inline(always)]
393    pub fn txdmaen(&mut self) -> TXDMAEN_W<CR2rs> {
394        TXDMAEN_W::new(self, 1)
395    }
396    ///Bit 2 - SS output enable
397    #[inline(always)]
398    pub fn ssoe(&mut self) -> SSOE_W<CR2rs> {
399        SSOE_W::new(self, 2)
400    }
401    ///Bit 5 - Error interrupt enable
402    #[inline(always)]
403    pub fn errie(&mut self) -> ERRIE_W<CR2rs> {
404        ERRIE_W::new(self, 5)
405    }
406    ///Bit 6 - RX buffer not empty interrupt enable
407    #[inline(always)]
408    pub fn rxneie(&mut self) -> RXNEIE_W<CR2rs> {
409        RXNEIE_W::new(self, 6)
410    }
411    ///Bit 7 - Tx buffer empty interrupt enable
412    #[inline(always)]
413    pub fn txeie(&mut self) -> TXEIE_W<CR2rs> {
414        TXEIE_W::new(self, 7)
415    }
416}
417/**control register 2
418
419You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
420
421See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1:CR2)*/
422pub struct CR2rs;
423impl crate::RegisterSpec for CR2rs {
424    type Ux = u16;
425}
426///`read()` method returns [`cr2::R`](R) reader structure
427impl crate::Readable for CR2rs {}
428///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
429impl crate::Writable for CR2rs {
430    type Safety = crate::Unsafe;
431}
432///`reset()` method sets CR2 to value 0
433impl crate::Resettable for CR2rs {}
stm32f1/stm32f107/spi1/cr2.rs

stm32f1/stm32f107/spi1/
cr2.rs
