stm32f1/stm32f107/sdio/
dctrl.rs

1///Register `DCTRL` reader
2pub type R = crate::R<DCTRLrs>;
3///Register `DCTRL` writer
4pub type W = crate::W<DCTRLrs>;
5/**DTEN
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DTEN {
11    ///0: Disabled
12    Disabled = 0,
13    ///1: Start transfer
14    Enabled = 1,
15}
16impl From<DTEN> for bool {
17    #[inline(always)]
18    fn from(variant: DTEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DTEN` reader - DTEN
23pub type DTEN_R = crate::BitReader<DTEN>;
24impl DTEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DTEN {
28        match self.bits {
29            false => DTEN::Disabled,
30            true => DTEN::Enabled,
31        }
32    }
33    ///Disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == DTEN::Disabled
37    }
38    ///Start transfer
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == DTEN::Enabled
42    }
43}
44///Field `DTEN` writer - DTEN
45pub type DTEN_W<'a, REG> = crate::BitWriter<'a, REG, DTEN>;
46impl<'a, REG> DTEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(DTEN::Disabled)
54    }
55    ///Start transfer
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(DTEN::Enabled)
59    }
60}
61/**Data transfer direction selection
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum DTDIR {
67    ///0: From controller to card
68    ControllerToCard = 0,
69    ///1: From card to controller
70    CardToController = 1,
71}
72impl From<DTDIR> for bool {
73    #[inline(always)]
74    fn from(variant: DTDIR) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `DTDIR` reader - Data transfer direction selection
79pub type DTDIR_R = crate::BitReader<DTDIR>;
80impl DTDIR_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> DTDIR {
84        match self.bits {
85            false => DTDIR::ControllerToCard,
86            true => DTDIR::CardToController,
87        }
88    }
89    ///From controller to card
90    #[inline(always)]
91    pub fn is_controller_to_card(&self) -> bool {
92        *self == DTDIR::ControllerToCard
93    }
94    ///From card to controller
95    #[inline(always)]
96    pub fn is_card_to_controller(&self) -> bool {
97        *self == DTDIR::CardToController
98    }
99}
100///Field `DTDIR` writer - Data transfer direction selection
101pub type DTDIR_W<'a, REG> = crate::BitWriter<'a, REG, DTDIR>;
102impl<'a, REG> DTDIR_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///From controller to card
107    #[inline(always)]
108    pub fn controller_to_card(self) -> &'a mut crate::W<REG> {
109        self.variant(DTDIR::ControllerToCard)
110    }
111    ///From card to controller
112    #[inline(always)]
113    pub fn card_to_controller(self) -> &'a mut crate::W<REG> {
114        self.variant(DTDIR::CardToController)
115    }
116}
117/**Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum DTMODE {
123    ///0: Bloack data transfer
124    BlockMode = 0,
125    ///1: Stream or SDIO multibyte data transfer
126    StreamMode = 1,
127}
128impl From<DTMODE> for bool {
129    #[inline(always)]
130    fn from(variant: DTMODE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `DTMODE` reader - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
135pub type DTMODE_R = crate::BitReader<DTMODE>;
136impl DTMODE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> DTMODE {
140        match self.bits {
141            false => DTMODE::BlockMode,
142            true => DTMODE::StreamMode,
143        }
144    }
145    ///Bloack data transfer
146    #[inline(always)]
147    pub fn is_block_mode(&self) -> bool {
148        *self == DTMODE::BlockMode
149    }
150    ///Stream or SDIO multibyte data transfer
151    #[inline(always)]
152    pub fn is_stream_mode(&self) -> bool {
153        *self == DTMODE::StreamMode
154    }
155}
156///Field `DTMODE` writer - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
157pub type DTMODE_W<'a, REG> = crate::BitWriter<'a, REG, DTMODE>;
158impl<'a, REG> DTMODE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Bloack data transfer
163    #[inline(always)]
164    pub fn block_mode(self) -> &'a mut crate::W<REG> {
165        self.variant(DTMODE::BlockMode)
166    }
167    ///Stream or SDIO multibyte data transfer
168    #[inline(always)]
169    pub fn stream_mode(self) -> &'a mut crate::W<REG> {
170        self.variant(DTMODE::StreamMode)
171    }
172}
173/**DMA enable bit
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum DMAEN {
179    ///0: Dma disabled
180    Disabled = 0,
181    ///1: Dma enabled
182    Enabled = 1,
183}
184impl From<DMAEN> for bool {
185    #[inline(always)]
186    fn from(variant: DMAEN) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `DMAEN` reader - DMA enable bit
191pub type DMAEN_R = crate::BitReader<DMAEN>;
192impl DMAEN_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> DMAEN {
196        match self.bits {
197            false => DMAEN::Disabled,
198            true => DMAEN::Enabled,
199        }
200    }
201    ///Dma disabled
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == DMAEN::Disabled
205    }
206    ///Dma enabled
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == DMAEN::Enabled
210    }
211}
212///Field `DMAEN` writer - DMA enable bit
213pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN>;
214impl<'a, REG> DMAEN_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Dma disabled
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(DMAEN::Disabled)
222    }
223    ///Dma enabled
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(DMAEN::Enabled)
227    }
228}
229///Field `DBLOCKSIZE` reader - Data block size
230pub type DBLOCKSIZE_R = crate::FieldReader;
231///Field `DBLOCKSIZE` writer - Data block size
232pub type DBLOCKSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
233/**Read wait start
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum RWSTART {
239    ///0: Don't start read wait operation
240    Disabled = 0,
241    ///1: Read wait operation starts
242    Enabled = 1,
243}
244impl From<RWSTART> for bool {
245    #[inline(always)]
246    fn from(variant: RWSTART) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `RWSTART` reader - Read wait start
251pub type RWSTART_R = crate::BitReader<RWSTART>;
252impl RWSTART_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> RWSTART {
256        match self.bits {
257            false => RWSTART::Disabled,
258            true => RWSTART::Enabled,
259        }
260    }
261    ///Don't start read wait operation
262    #[inline(always)]
263    pub fn is_disabled(&self) -> bool {
264        *self == RWSTART::Disabled
265    }
266    ///Read wait operation starts
267    #[inline(always)]
268    pub fn is_enabled(&self) -> bool {
269        *self == RWSTART::Enabled
270    }
271}
272///Field `RWSTART` writer - Read wait start
273pub type RWSTART_W<'a, REG> = crate::BitWriter<'a, REG, RWSTART>;
274impl<'a, REG> RWSTART_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///Don't start read wait operation
279    #[inline(always)]
280    pub fn disabled(self) -> &'a mut crate::W<REG> {
281        self.variant(RWSTART::Disabled)
282    }
283    ///Read wait operation starts
284    #[inline(always)]
285    pub fn enabled(self) -> &'a mut crate::W<REG> {
286        self.variant(RWSTART::Enabled)
287    }
288}
289/**Read wait stop
290
291Value on reset: 0*/
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum RWSTOP {
295    ///0: Read wait in progress if RWSTART is enabled
296    Disabled = 0,
297    ///1: Enable for read wait stop if RWSTART is enabled
298    Enabled = 1,
299}
300impl From<RWSTOP> for bool {
301    #[inline(always)]
302    fn from(variant: RWSTOP) -> Self {
303        variant as u8 != 0
304    }
305}
306///Field `RWSTOP` reader - Read wait stop
307pub type RWSTOP_R = crate::BitReader<RWSTOP>;
308impl RWSTOP_R {
309    ///Get enumerated values variant
310    #[inline(always)]
311    pub const fn variant(&self) -> RWSTOP {
312        match self.bits {
313            false => RWSTOP::Disabled,
314            true => RWSTOP::Enabled,
315        }
316    }
317    ///Read wait in progress if RWSTART is enabled
318    #[inline(always)]
319    pub fn is_disabled(&self) -> bool {
320        *self == RWSTOP::Disabled
321    }
322    ///Enable for read wait stop if RWSTART is enabled
323    #[inline(always)]
324    pub fn is_enabled(&self) -> bool {
325        *self == RWSTOP::Enabled
326    }
327}
328///Field `RWSTOP` writer - Read wait stop
329pub type RWSTOP_W<'a, REG> = crate::BitWriter<'a, REG, RWSTOP>;
330impl<'a, REG> RWSTOP_W<'a, REG>
331where
332    REG: crate::Writable + crate::RegisterSpec,
333{
334    ///Read wait in progress if RWSTART is enabled
335    #[inline(always)]
336    pub fn disabled(self) -> &'a mut crate::W<REG> {
337        self.variant(RWSTOP::Disabled)
338    }
339    ///Enable for read wait stop if RWSTART is enabled
340    #[inline(always)]
341    pub fn enabled(self) -> &'a mut crate::W<REG> {
342        self.variant(RWSTOP::Enabled)
343    }
344}
345/**Read wait mode
346
347Value on reset: 0*/
348#[cfg_attr(feature = "defmt", derive(defmt::Format))]
349#[derive(Clone, Copy, Debug, PartialEq, Eq)]
350pub enum RWMOD {
351    ///0: Read wait control stopping using SDIO_D2
352    D2 = 0,
353    ///1: Read wait control using SDIO_CK
354    Ck = 1,
355}
356impl From<RWMOD> for bool {
357    #[inline(always)]
358    fn from(variant: RWMOD) -> Self {
359        variant as u8 != 0
360    }
361}
362///Field `RWMOD` reader - Read wait mode
363pub type RWMOD_R = crate::BitReader<RWMOD>;
364impl RWMOD_R {
365    ///Get enumerated values variant
366    #[inline(always)]
367    pub const fn variant(&self) -> RWMOD {
368        match self.bits {
369            false => RWMOD::D2,
370            true => RWMOD::Ck,
371        }
372    }
373    ///Read wait control stopping using SDIO_D2
374    #[inline(always)]
375    pub fn is_d2(&self) -> bool {
376        *self == RWMOD::D2
377    }
378    ///Read wait control using SDIO_CK
379    #[inline(always)]
380    pub fn is_ck(&self) -> bool {
381        *self == RWMOD::Ck
382    }
383}
384///Field `RWMOD` writer - Read wait mode
385pub type RWMOD_W<'a, REG> = crate::BitWriter<'a, REG, RWMOD>;
386impl<'a, REG> RWMOD_W<'a, REG>
387where
388    REG: crate::Writable + crate::RegisterSpec,
389{
390    ///Read wait control stopping using SDIO_D2
391    #[inline(always)]
392    pub fn d2(self) -> &'a mut crate::W<REG> {
393        self.variant(RWMOD::D2)
394    }
395    ///Read wait control using SDIO_CK
396    #[inline(always)]
397    pub fn ck(self) -> &'a mut crate::W<REG> {
398        self.variant(RWMOD::Ck)
399    }
400}
401/**SD I/O enable functions
402
403Value on reset: 0*/
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum SDIOEN {
407    ///0: SDIO operations disabled
408    Disabled = 0,
409    ///1: SDIO operations enabled
410    Enabled = 1,
411}
412impl From<SDIOEN> for bool {
413    #[inline(always)]
414    fn from(variant: SDIOEN) -> Self {
415        variant as u8 != 0
416    }
417}
418///Field `SDIOEN` reader - SD I/O enable functions
419pub type SDIOEN_R = crate::BitReader<SDIOEN>;
420impl SDIOEN_R {
421    ///Get enumerated values variant
422    #[inline(always)]
423    pub const fn variant(&self) -> SDIOEN {
424        match self.bits {
425            false => SDIOEN::Disabled,
426            true => SDIOEN::Enabled,
427        }
428    }
429    ///SDIO operations disabled
430    #[inline(always)]
431    pub fn is_disabled(&self) -> bool {
432        *self == SDIOEN::Disabled
433    }
434    ///SDIO operations enabled
435    #[inline(always)]
436    pub fn is_enabled(&self) -> bool {
437        *self == SDIOEN::Enabled
438    }
439}
440///Field `SDIOEN` writer - SD I/O enable functions
441pub type SDIOEN_W<'a, REG> = crate::BitWriter<'a, REG, SDIOEN>;
442impl<'a, REG> SDIOEN_W<'a, REG>
443where
444    REG: crate::Writable + crate::RegisterSpec,
445{
446    ///SDIO operations disabled
447    #[inline(always)]
448    pub fn disabled(self) -> &'a mut crate::W<REG> {
449        self.variant(SDIOEN::Disabled)
450    }
451    ///SDIO operations enabled
452    #[inline(always)]
453    pub fn enabled(self) -> &'a mut crate::W<REG> {
454        self.variant(SDIOEN::Enabled)
455    }
456}
457impl R {
458    ///Bit 0 - DTEN
459    #[inline(always)]
460    pub fn dten(&self) -> DTEN_R {
461        DTEN_R::new((self.bits & 1) != 0)
462    }
463    ///Bit 1 - Data transfer direction selection
464    #[inline(always)]
465    pub fn dtdir(&self) -> DTDIR_R {
466        DTDIR_R::new(((self.bits >> 1) & 1) != 0)
467    }
468    ///Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
469    #[inline(always)]
470    pub fn dtmode(&self) -> DTMODE_R {
471        DTMODE_R::new(((self.bits >> 2) & 1) != 0)
472    }
473    ///Bit 3 - DMA enable bit
474    #[inline(always)]
475    pub fn dmaen(&self) -> DMAEN_R {
476        DMAEN_R::new(((self.bits >> 3) & 1) != 0)
477    }
478    ///Bits 4:7 - Data block size
479    #[inline(always)]
480    pub fn dblocksize(&self) -> DBLOCKSIZE_R {
481        DBLOCKSIZE_R::new(((self.bits >> 4) & 0x0f) as u8)
482    }
483    ///Bit 8 - Read wait start
484    #[inline(always)]
485    pub fn rwstart(&self) -> RWSTART_R {
486        RWSTART_R::new(((self.bits >> 8) & 1) != 0)
487    }
488    ///Bit 9 - Read wait stop
489    #[inline(always)]
490    pub fn rwstop(&self) -> RWSTOP_R {
491        RWSTOP_R::new(((self.bits >> 9) & 1) != 0)
492    }
493    ///Bit 10 - Read wait mode
494    #[inline(always)]
495    pub fn rwmod(&self) -> RWMOD_R {
496        RWMOD_R::new(((self.bits >> 10) & 1) != 0)
497    }
498    ///Bit 11 - SD I/O enable functions
499    #[inline(always)]
500    pub fn sdioen(&self) -> SDIOEN_R {
501        SDIOEN_R::new(((self.bits >> 11) & 1) != 0)
502    }
503}
504impl core::fmt::Debug for R {
505    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
506        f.debug_struct("DCTRL")
507            .field("sdioen", &self.sdioen())
508            .field("rwmod", &self.rwmod())
509            .field("rwstop", &self.rwstop())
510            .field("rwstart", &self.rwstart())
511            .field("dblocksize", &self.dblocksize())
512            .field("dmaen", &self.dmaen())
513            .field("dtmode", &self.dtmode())
514            .field("dtdir", &self.dtdir())
515            .field("dten", &self.dten())
516            .finish()
517    }
518}
519impl W {
520    ///Bit 0 - DTEN
521    #[inline(always)]
522    pub fn dten(&mut self) -> DTEN_W<DCTRLrs> {
523        DTEN_W::new(self, 0)
524    }
525    ///Bit 1 - Data transfer direction selection
526    #[inline(always)]
527    pub fn dtdir(&mut self) -> DTDIR_W<DCTRLrs> {
528        DTDIR_W::new(self, 1)
529    }
530    ///Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
531    #[inline(always)]
532    pub fn dtmode(&mut self) -> DTMODE_W<DCTRLrs> {
533        DTMODE_W::new(self, 2)
534    }
535    ///Bit 3 - DMA enable bit
536    #[inline(always)]
537    pub fn dmaen(&mut self) -> DMAEN_W<DCTRLrs> {
538        DMAEN_W::new(self, 3)
539    }
540    ///Bits 4:7 - Data block size
541    #[inline(always)]
542    pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<DCTRLrs> {
543        DBLOCKSIZE_W::new(self, 4)
544    }
545    ///Bit 8 - Read wait start
546    #[inline(always)]
547    pub fn rwstart(&mut self) -> RWSTART_W<DCTRLrs> {
548        RWSTART_W::new(self, 8)
549    }
550    ///Bit 9 - Read wait stop
551    #[inline(always)]
552    pub fn rwstop(&mut self) -> RWSTOP_W<DCTRLrs> {
553        RWSTOP_W::new(self, 9)
554    }
555    ///Bit 10 - Read wait mode
556    #[inline(always)]
557    pub fn rwmod(&mut self) -> RWMOD_W<DCTRLrs> {
558        RWMOD_W::new(self, 10)
559    }
560    ///Bit 11 - SD I/O enable functions
561    #[inline(always)]
562    pub fn sdioen(&mut self) -> SDIOEN_W<DCTRLrs> {
563        SDIOEN_W::new(self, 11)
564    }
565}
566/**data control register
567
568You can [`read`](crate::Reg::read) this register and get [`dctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
569
570See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:DCTRL)*/
571pub struct DCTRLrs;
572impl crate::RegisterSpec for DCTRLrs {
573    type Ux = u32;
574}
575///`read()` method returns [`dctrl::R`](R) reader structure
576impl crate::Readable for DCTRLrs {}
577///`write(|w| ..)` method takes [`dctrl::W`](W) writer structure
578impl crate::Writable for DCTRLrs {
579    type Safety = crate::Unsafe;
580}
581///`reset()` method sets DCTRL to value 0
582impl crate::Resettable for DCTRLrs {}
stm32f1/stm32f107/sdio/dctrl.rs

stm32f1/stm32f107/sdio/
dctrl.rs
