stm32f1/stm32f107/exti/
imr.rs

1///Register `IMR` reader
2pub type R = crate::R<IMRrs>;
3///Register `IMR` writer
4pub type W = crate::W<IMRrs>;
5/**Interrupt Mask on line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum INTERRUPT_MASK {
11    ///0: Interrupt request line is masked
12    Masked = 0,
13    ///1: Interrupt request line is unmasked
14    Unmasked = 1,
15}
16impl From<INTERRUPT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: INTERRUPT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MR(0-19)` reader - Interrupt Mask on line %s
23pub type MR_R = crate::BitReader<INTERRUPT_MASK>;
24impl MR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> INTERRUPT_MASK {
28        match self.bits {
29            false => INTERRUPT_MASK::Masked,
30            true => INTERRUPT_MASK::Unmasked,
31        }
32    }
33    ///Interrupt request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == INTERRUPT_MASK::Masked
37    }
38    ///Interrupt request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == INTERRUPT_MASK::Unmasked
42    }
43}
44///Field `MR(0-19)` writer - Interrupt Mask on line %s
45pub type MR_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_MASK>;
46impl<'a, REG> MR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(INTERRUPT_MASK::Masked)
54    }
55    ///Interrupt request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(INTERRUPT_MASK::Unmasked)
59    }
60}
61impl R {
62    ///Interrupt Mask on line (0-19)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
65    #[inline(always)]
66    pub fn mr(&self, n: u8) -> MR_R {
67        #[allow(clippy::no_effect)]
68        [(); 20][n as usize];
69        MR_R::new(((self.bits >> n) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///Interrupt Mask on line (0-19)
73    #[inline(always)]
74    pub fn mr_iter(&self) -> impl Iterator<Item = MR_R> + '_ {
75        (0..20).map(move |n| MR_R::new(((self.bits >> n) & 1) != 0))
76    }
77    ///Bit 0 - Interrupt Mask on line 0
78    #[inline(always)]
79    pub fn mr0(&self) -> MR_R {
80        MR_R::new((self.bits & 1) != 0)
81    }
82    ///Bit 1 - Interrupt Mask on line 1
83    #[inline(always)]
84    pub fn mr1(&self) -> MR_R {
85        MR_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    ///Bit 2 - Interrupt Mask on line 2
88    #[inline(always)]
89    pub fn mr2(&self) -> MR_R {
90        MR_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    ///Bit 3 - Interrupt Mask on line 3
93    #[inline(always)]
94    pub fn mr3(&self) -> MR_R {
95        MR_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    ///Bit 4 - Interrupt Mask on line 4
98    #[inline(always)]
99    pub fn mr4(&self) -> MR_R {
100        MR_R::new(((self.bits >> 4) & 1) != 0)
101    }
102    ///Bit 5 - Interrupt Mask on line 5
103    #[inline(always)]
104    pub fn mr5(&self) -> MR_R {
105        MR_R::new(((self.bits >> 5) & 1) != 0)
106    }
107    ///Bit 6 - Interrupt Mask on line 6
108    #[inline(always)]
109    pub fn mr6(&self) -> MR_R {
110        MR_R::new(((self.bits >> 6) & 1) != 0)
111    }
112    ///Bit 7 - Interrupt Mask on line 7
113    #[inline(always)]
114    pub fn mr7(&self) -> MR_R {
115        MR_R::new(((self.bits >> 7) & 1) != 0)
116    }
117    ///Bit 8 - Interrupt Mask on line 8
118    #[inline(always)]
119    pub fn mr8(&self) -> MR_R {
120        MR_R::new(((self.bits >> 8) & 1) != 0)
121    }
122    ///Bit 9 - Interrupt Mask on line 9
123    #[inline(always)]
124    pub fn mr9(&self) -> MR_R {
125        MR_R::new(((self.bits >> 9) & 1) != 0)
126    }
127    ///Bit 10 - Interrupt Mask on line 10
128    #[inline(always)]
129    pub fn mr10(&self) -> MR_R {
130        MR_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 11 - Interrupt Mask on line 11
133    #[inline(always)]
134    pub fn mr11(&self) -> MR_R {
135        MR_R::new(((self.bits >> 11) & 1) != 0)
136    }
137    ///Bit 12 - Interrupt Mask on line 12
138    #[inline(always)]
139    pub fn mr12(&self) -> MR_R {
140        MR_R::new(((self.bits >> 12) & 1) != 0)
141    }
142    ///Bit 13 - Interrupt Mask on line 13
143    #[inline(always)]
144    pub fn mr13(&self) -> MR_R {
145        MR_R::new(((self.bits >> 13) & 1) != 0)
146    }
147    ///Bit 14 - Interrupt Mask on line 14
148    #[inline(always)]
149    pub fn mr14(&self) -> MR_R {
150        MR_R::new(((self.bits >> 14) & 1) != 0)
151    }
152    ///Bit 15 - Interrupt Mask on line 15
153    #[inline(always)]
154    pub fn mr15(&self) -> MR_R {
155        MR_R::new(((self.bits >> 15) & 1) != 0)
156    }
157    ///Bit 16 - Interrupt Mask on line 16
158    #[inline(always)]
159    pub fn mr16(&self) -> MR_R {
160        MR_R::new(((self.bits >> 16) & 1) != 0)
161    }
162    ///Bit 17 - Interrupt Mask on line 17
163    #[inline(always)]
164    pub fn mr17(&self) -> MR_R {
165        MR_R::new(((self.bits >> 17) & 1) != 0)
166    }
167    ///Bit 18 - Interrupt Mask on line 18
168    #[inline(always)]
169    pub fn mr18(&self) -> MR_R {
170        MR_R::new(((self.bits >> 18) & 1) != 0)
171    }
172    ///Bit 19 - Interrupt Mask on line 19
173    #[inline(always)]
174    pub fn mr19(&self) -> MR_R {
175        MR_R::new(((self.bits >> 19) & 1) != 0)
176    }
177}
178impl core::fmt::Debug for R {
179    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
180        f.debug_struct("IMR")
181            .field("mr0", &self.mr0())
182            .field("mr1", &self.mr1())
183            .field("mr2", &self.mr2())
184            .field("mr3", &self.mr3())
185            .field("mr4", &self.mr4())
186            .field("mr5", &self.mr5())
187            .field("mr6", &self.mr6())
188            .field("mr7", &self.mr7())
189            .field("mr8", &self.mr8())
190            .field("mr9", &self.mr9())
191            .field("mr10", &self.mr10())
192            .field("mr11", &self.mr11())
193            .field("mr12", &self.mr12())
194            .field("mr13", &self.mr13())
195            .field("mr14", &self.mr14())
196            .field("mr15", &self.mr15())
197            .field("mr16", &self.mr16())
198            .field("mr17", &self.mr17())
199            .field("mr18", &self.mr18())
200            .field("mr19", &self.mr19())
201            .finish()
202    }
203}
204impl W {
205    ///Interrupt Mask on line (0-19)
206    ///
207    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
208    #[inline(always)]
209    pub fn mr(&mut self, n: u8) -> MR_W<IMRrs> {
210        #[allow(clippy::no_effect)]
211        [(); 20][n as usize];
212        MR_W::new(self, n)
213    }
214    ///Bit 0 - Interrupt Mask on line 0
215    #[inline(always)]
216    pub fn mr0(&mut self) -> MR_W<IMRrs> {
217        MR_W::new(self, 0)
218    }
219    ///Bit 1 - Interrupt Mask on line 1
220    #[inline(always)]
221    pub fn mr1(&mut self) -> MR_W<IMRrs> {
222        MR_W::new(self, 1)
223    }
224    ///Bit 2 - Interrupt Mask on line 2
225    #[inline(always)]
226    pub fn mr2(&mut self) -> MR_W<IMRrs> {
227        MR_W::new(self, 2)
228    }
229    ///Bit 3 - Interrupt Mask on line 3
230    #[inline(always)]
231    pub fn mr3(&mut self) -> MR_W<IMRrs> {
232        MR_W::new(self, 3)
233    }
234    ///Bit 4 - Interrupt Mask on line 4
235    #[inline(always)]
236    pub fn mr4(&mut self) -> MR_W<IMRrs> {
237        MR_W::new(self, 4)
238    }
239    ///Bit 5 - Interrupt Mask on line 5
240    #[inline(always)]
241    pub fn mr5(&mut self) -> MR_W<IMRrs> {
242        MR_W::new(self, 5)
243    }
244    ///Bit 6 - Interrupt Mask on line 6
245    #[inline(always)]
246    pub fn mr6(&mut self) -> MR_W<IMRrs> {
247        MR_W::new(self, 6)
248    }
249    ///Bit 7 - Interrupt Mask on line 7
250    #[inline(always)]
251    pub fn mr7(&mut self) -> MR_W<IMRrs> {
252        MR_W::new(self, 7)
253    }
254    ///Bit 8 - Interrupt Mask on line 8
255    #[inline(always)]
256    pub fn mr8(&mut self) -> MR_W<IMRrs> {
257        MR_W::new(self, 8)
258    }
259    ///Bit 9 - Interrupt Mask on line 9
260    #[inline(always)]
261    pub fn mr9(&mut self) -> MR_W<IMRrs> {
262        MR_W::new(self, 9)
263    }
264    ///Bit 10 - Interrupt Mask on line 10
265    #[inline(always)]
266    pub fn mr10(&mut self) -> MR_W<IMRrs> {
267        MR_W::new(self, 10)
268    }
269    ///Bit 11 - Interrupt Mask on line 11
270    #[inline(always)]
271    pub fn mr11(&mut self) -> MR_W<IMRrs> {
272        MR_W::new(self, 11)
273    }
274    ///Bit 12 - Interrupt Mask on line 12
275    #[inline(always)]
276    pub fn mr12(&mut self) -> MR_W<IMRrs> {
277        MR_W::new(self, 12)
278    }
279    ///Bit 13 - Interrupt Mask on line 13
280    #[inline(always)]
281    pub fn mr13(&mut self) -> MR_W<IMRrs> {
282        MR_W::new(self, 13)
283    }
284    ///Bit 14 - Interrupt Mask on line 14
285    #[inline(always)]
286    pub fn mr14(&mut self) -> MR_W<IMRrs> {
287        MR_W::new(self, 14)
288    }
289    ///Bit 15 - Interrupt Mask on line 15
290    #[inline(always)]
291    pub fn mr15(&mut self) -> MR_W<IMRrs> {
292        MR_W::new(self, 15)
293    }
294    ///Bit 16 - Interrupt Mask on line 16
295    #[inline(always)]
296    pub fn mr16(&mut self) -> MR_W<IMRrs> {
297        MR_W::new(self, 16)
298    }
299    ///Bit 17 - Interrupt Mask on line 17
300    #[inline(always)]
301    pub fn mr17(&mut self) -> MR_W<IMRrs> {
302        MR_W::new(self, 17)
303    }
304    ///Bit 18 - Interrupt Mask on line 18
305    #[inline(always)]
306    pub fn mr18(&mut self) -> MR_W<IMRrs> {
307        MR_W::new(self, 18)
308    }
309    ///Bit 19 - Interrupt Mask on line 19
310    #[inline(always)]
311    pub fn mr19(&mut self) -> MR_W<IMRrs> {
312        MR_W::new(self, 19)
313    }
314}
315/**Interrupt mask register (EXTI_IMR)
316
317You can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
318
319See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#EXTI:IMR)*/
320pub struct IMRrs;
321impl crate::RegisterSpec for IMRrs {
322    type Ux = u32;
323}
324///`read()` method returns [`imr::R`](R) reader structure
325impl crate::Readable for IMRrs {}
326///`write(|w| ..)` method takes [`imr::W`](W) writer structure
327impl crate::Writable for IMRrs {
328    type Safety = crate::Unsafe;
329}
330///`reset()` method sets IMR to value 0
331impl crate::Resettable for IMRrs {}
stm32f1/stm32f107/exti/imr.rs

stm32f1/stm32f107/exti/
imr.rs
