stm32f1/stm32f107/dma1/
isr.rs

1///Register `ISR` reader
2pub type R = crate::R<ISRrs>;
3/**Channel %s Global interrupt flag
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum GIF1 {
9    ///0: No transfer error, half event, complete event
10    NoEvent = 0,
11    ///1: A transfer error, half event or complete event has occured
12    Event = 1,
13}
14impl From<GIF1> for bool {
15    #[inline(always)]
16    fn from(variant: GIF1) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `GIF(1-7)` reader - Channel %s Global interrupt flag
21pub type GIF_R = crate::BitReader<GIF1>;
22impl GIF_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> GIF1 {
26        match self.bits {
27            false => GIF1::NoEvent,
28            true => GIF1::Event,
29        }
30    }
31    ///No transfer error, half event, complete event
32    #[inline(always)]
33    pub fn is_no_event(&self) -> bool {
34        *self == GIF1::NoEvent
35    }
36    ///A transfer error, half event or complete event has occured
37    #[inline(always)]
38    pub fn is_event(&self) -> bool {
39        *self == GIF1::Event
40    }
41}
42/**Channel %s Transfer Complete flag
43
44Value on reset: 0*/
45#[cfg_attr(feature = "defmt", derive(defmt::Format))]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum TCIF1 {
48    ///0: No transfer complete event
49    NotComplete = 0,
50    ///1: A transfer complete event has occured
51    Complete = 1,
52}
53impl From<TCIF1> for bool {
54    #[inline(always)]
55    fn from(variant: TCIF1) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `TCIF(1-7)` reader - Channel %s Transfer Complete flag
60pub type TCIF_R = crate::BitReader<TCIF1>;
61impl TCIF_R {
62    ///Get enumerated values variant
63    #[inline(always)]
64    pub const fn variant(&self) -> TCIF1 {
65        match self.bits {
66            false => TCIF1::NotComplete,
67            true => TCIF1::Complete,
68        }
69    }
70    ///No transfer complete event
71    #[inline(always)]
72    pub fn is_not_complete(&self) -> bool {
73        *self == TCIF1::NotComplete
74    }
75    ///A transfer complete event has occured
76    #[inline(always)]
77    pub fn is_complete(&self) -> bool {
78        *self == TCIF1::Complete
79    }
80}
81/**Channel %s Half Transfer Complete flag
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum HTIF1 {
87    ///0: No half transfer event
88    NotHalf = 0,
89    ///1: A half transfer event has occured
90    Half = 1,
91}
92impl From<HTIF1> for bool {
93    #[inline(always)]
94    fn from(variant: HTIF1) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `HTIF(1-7)` reader - Channel %s Half Transfer Complete flag
99pub type HTIF_R = crate::BitReader<HTIF1>;
100impl HTIF_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> HTIF1 {
104        match self.bits {
105            false => HTIF1::NotHalf,
106            true => HTIF1::Half,
107        }
108    }
109    ///No half transfer event
110    #[inline(always)]
111    pub fn is_not_half(&self) -> bool {
112        *self == HTIF1::NotHalf
113    }
114    ///A half transfer event has occured
115    #[inline(always)]
116    pub fn is_half(&self) -> bool {
117        *self == HTIF1::Half
118    }
119}
120/**Channel %s Transfer Error flag
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum TEIF1 {
126    ///0: No transfer error
127    NoError = 0,
128    ///1: A transfer error has occured
129    Error = 1,
130}
131impl From<TEIF1> for bool {
132    #[inline(always)]
133    fn from(variant: TEIF1) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `TEIF(1-7)` reader - Channel %s Transfer Error flag
138pub type TEIF_R = crate::BitReader<TEIF1>;
139impl TEIF_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> TEIF1 {
143        match self.bits {
144            false => TEIF1::NoError,
145            true => TEIF1::Error,
146        }
147    }
148    ///No transfer error
149    #[inline(always)]
150    pub fn is_no_error(&self) -> bool {
151        *self == TEIF1::NoError
152    }
153    ///A transfer error has occured
154    #[inline(always)]
155    pub fn is_error(&self) -> bool {
156        *self == TEIF1::Error
157    }
158}
159impl R {
160    ///Channel (1-7) Global interrupt flag
161    ///
162    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `GIF1` field.</div>
163    #[inline(always)]
164    pub fn gif(&self, n: u8) -> GIF_R {
165        #[allow(clippy::no_effect)]
166        [(); 7][n as usize];
167        GIF_R::new(((self.bits >> (n * 4)) & 1) != 0)
168    }
169    ///Iterator for array of:
170    ///Channel (1-7) Global interrupt flag
171    #[inline(always)]
172    pub fn gif_iter(&self) -> impl Iterator<Item = GIF_R> + '_ {
173        (0..7).map(move |n| GIF_R::new(((self.bits >> (n * 4)) & 1) != 0))
174    }
175    ///Bit 0 - Channel 1 Global interrupt flag
176    #[inline(always)]
177    pub fn gif1(&self) -> GIF_R {
178        GIF_R::new((self.bits & 1) != 0)
179    }
180    ///Bit 4 - Channel 2 Global interrupt flag
181    #[inline(always)]
182    pub fn gif2(&self) -> GIF_R {
183        GIF_R::new(((self.bits >> 4) & 1) != 0)
184    }
185    ///Bit 8 - Channel 3 Global interrupt flag
186    #[inline(always)]
187    pub fn gif3(&self) -> GIF_R {
188        GIF_R::new(((self.bits >> 8) & 1) != 0)
189    }
190    ///Bit 12 - Channel 4 Global interrupt flag
191    #[inline(always)]
192    pub fn gif4(&self) -> GIF_R {
193        GIF_R::new(((self.bits >> 12) & 1) != 0)
194    }
195    ///Bit 16 - Channel 5 Global interrupt flag
196    #[inline(always)]
197    pub fn gif5(&self) -> GIF_R {
198        GIF_R::new(((self.bits >> 16) & 1) != 0)
199    }
200    ///Bit 20 - Channel 6 Global interrupt flag
201    #[inline(always)]
202    pub fn gif6(&self) -> GIF_R {
203        GIF_R::new(((self.bits >> 20) & 1) != 0)
204    }
205    ///Bit 24 - Channel 7 Global interrupt flag
206    #[inline(always)]
207    pub fn gif7(&self) -> GIF_R {
208        GIF_R::new(((self.bits >> 24) & 1) != 0)
209    }
210    ///Channel (1-7) Transfer Complete flag
211    ///
212    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TCIF1` field.</div>
213    #[inline(always)]
214    pub fn tcif(&self, n: u8) -> TCIF_R {
215        #[allow(clippy::no_effect)]
216        [(); 7][n as usize];
217        TCIF_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
218    }
219    ///Iterator for array of:
220    ///Channel (1-7) Transfer Complete flag
221    #[inline(always)]
222    pub fn tcif_iter(&self) -> impl Iterator<Item = TCIF_R> + '_ {
223        (0..7).map(move |n| TCIF_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
224    }
225    ///Bit 1 - Channel 1 Transfer Complete flag
226    #[inline(always)]
227    pub fn tcif1(&self) -> TCIF_R {
228        TCIF_R::new(((self.bits >> 1) & 1) != 0)
229    }
230    ///Bit 5 - Channel 2 Transfer Complete flag
231    #[inline(always)]
232    pub fn tcif2(&self) -> TCIF_R {
233        TCIF_R::new(((self.bits >> 5) & 1) != 0)
234    }
235    ///Bit 9 - Channel 3 Transfer Complete flag
236    #[inline(always)]
237    pub fn tcif3(&self) -> TCIF_R {
238        TCIF_R::new(((self.bits >> 9) & 1) != 0)
239    }
240    ///Bit 13 - Channel 4 Transfer Complete flag
241    #[inline(always)]
242    pub fn tcif4(&self) -> TCIF_R {
243        TCIF_R::new(((self.bits >> 13) & 1) != 0)
244    }
245    ///Bit 17 - Channel 5 Transfer Complete flag
246    #[inline(always)]
247    pub fn tcif5(&self) -> TCIF_R {
248        TCIF_R::new(((self.bits >> 17) & 1) != 0)
249    }
250    ///Bit 21 - Channel 6 Transfer Complete flag
251    #[inline(always)]
252    pub fn tcif6(&self) -> TCIF_R {
253        TCIF_R::new(((self.bits >> 21) & 1) != 0)
254    }
255    ///Bit 25 - Channel 7 Transfer Complete flag
256    #[inline(always)]
257    pub fn tcif7(&self) -> TCIF_R {
258        TCIF_R::new(((self.bits >> 25) & 1) != 0)
259    }
260    ///Channel (1-7) Half Transfer Complete flag
261    ///
262    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `HTIF1` field.</div>
263    #[inline(always)]
264    pub fn htif(&self, n: u8) -> HTIF_R {
265        #[allow(clippy::no_effect)]
266        [(); 7][n as usize];
267        HTIF_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0)
268    }
269    ///Iterator for array of:
270    ///Channel (1-7) Half Transfer Complete flag
271    #[inline(always)]
272    pub fn htif_iter(&self) -> impl Iterator<Item = HTIF_R> + '_ {
273        (0..7).map(move |n| HTIF_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0))
274    }
275    ///Bit 2 - Channel 1 Half Transfer Complete flag
276    #[inline(always)]
277    pub fn htif1(&self) -> HTIF_R {
278        HTIF_R::new(((self.bits >> 2) & 1) != 0)
279    }
280    ///Bit 6 - Channel 2 Half Transfer Complete flag
281    #[inline(always)]
282    pub fn htif2(&self) -> HTIF_R {
283        HTIF_R::new(((self.bits >> 6) & 1) != 0)
284    }
285    ///Bit 10 - Channel 3 Half Transfer Complete flag
286    #[inline(always)]
287    pub fn htif3(&self) -> HTIF_R {
288        HTIF_R::new(((self.bits >> 10) & 1) != 0)
289    }
290    ///Bit 14 - Channel 4 Half Transfer Complete flag
291    #[inline(always)]
292    pub fn htif4(&self) -> HTIF_R {
293        HTIF_R::new(((self.bits >> 14) & 1) != 0)
294    }
295    ///Bit 18 - Channel 5 Half Transfer Complete flag
296    #[inline(always)]
297    pub fn htif5(&self) -> HTIF_R {
298        HTIF_R::new(((self.bits >> 18) & 1) != 0)
299    }
300    ///Bit 22 - Channel 6 Half Transfer Complete flag
301    #[inline(always)]
302    pub fn htif6(&self) -> HTIF_R {
303        HTIF_R::new(((self.bits >> 22) & 1) != 0)
304    }
305    ///Bit 26 - Channel 7 Half Transfer Complete flag
306    #[inline(always)]
307    pub fn htif7(&self) -> HTIF_R {
308        HTIF_R::new(((self.bits >> 26) & 1) != 0)
309    }
310    ///Channel (1-7) Transfer Error flag
311    ///
312    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TEIF1` field.</div>
313    #[inline(always)]
314    pub fn teif(&self, n: u8) -> TEIF_R {
315        #[allow(clippy::no_effect)]
316        [(); 7][n as usize];
317        TEIF_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
318    }
319    ///Iterator for array of:
320    ///Channel (1-7) Transfer Error flag
321    #[inline(always)]
322    pub fn teif_iter(&self) -> impl Iterator<Item = TEIF_R> + '_ {
323        (0..7).map(move |n| TEIF_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
324    }
325    ///Bit 3 - Channel 1 Transfer Error flag
326    #[inline(always)]
327    pub fn teif1(&self) -> TEIF_R {
328        TEIF_R::new(((self.bits >> 3) & 1) != 0)
329    }
330    ///Bit 7 - Channel 2 Transfer Error flag
331    #[inline(always)]
332    pub fn teif2(&self) -> TEIF_R {
333        TEIF_R::new(((self.bits >> 7) & 1) != 0)
334    }
335    ///Bit 11 - Channel 3 Transfer Error flag
336    #[inline(always)]
337    pub fn teif3(&self) -> TEIF_R {
338        TEIF_R::new(((self.bits >> 11) & 1) != 0)
339    }
340    ///Bit 15 - Channel 4 Transfer Error flag
341    #[inline(always)]
342    pub fn teif4(&self) -> TEIF_R {
343        TEIF_R::new(((self.bits >> 15) & 1) != 0)
344    }
345    ///Bit 19 - Channel 5 Transfer Error flag
346    #[inline(always)]
347    pub fn teif5(&self) -> TEIF_R {
348        TEIF_R::new(((self.bits >> 19) & 1) != 0)
349    }
350    ///Bit 23 - Channel 6 Transfer Error flag
351    #[inline(always)]
352    pub fn teif6(&self) -> TEIF_R {
353        TEIF_R::new(((self.bits >> 23) & 1) != 0)
354    }
355    ///Bit 27 - Channel 7 Transfer Error flag
356    #[inline(always)]
357    pub fn teif7(&self) -> TEIF_R {
358        TEIF_R::new(((self.bits >> 27) & 1) != 0)
359    }
360}
361impl core::fmt::Debug for R {
362    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
363        f.debug_struct("ISR")
364            .field("gif1", &self.gif1())
365            .field("gif2", &self.gif2())
366            .field("gif3", &self.gif3())
367            .field("gif4", &self.gif4())
368            .field("gif5", &self.gif5())
369            .field("gif6", &self.gif6())
370            .field("gif7", &self.gif7())
371            .field("tcif1", &self.tcif1())
372            .field("tcif2", &self.tcif2())
373            .field("tcif3", &self.tcif3())
374            .field("tcif4", &self.tcif4())
375            .field("tcif5", &self.tcif5())
376            .field("tcif6", &self.tcif6())
377            .field("tcif7", &self.tcif7())
378            .field("htif1", &self.htif1())
379            .field("htif2", &self.htif2())
380            .field("htif3", &self.htif3())
381            .field("htif4", &self.htif4())
382            .field("htif5", &self.htif5())
383            .field("htif6", &self.htif6())
384            .field("htif7", &self.htif7())
385            .field("teif1", &self.teif1())
386            .field("teif2", &self.teif2())
387            .field("teif3", &self.teif3())
388            .field("teif4", &self.teif4())
389            .field("teif5", &self.teif5())
390            .field("teif6", &self.teif6())
391            .field("teif7", &self.teif7())
392            .finish()
393    }
394}
395/**DMA interrupt status register (DMA_ISR)
396
397You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
398
399See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DMA1:ISR)*/
400pub struct ISRrs;
401impl crate::RegisterSpec for ISRrs {
402    type Ux = u32;
403}
404///`read()` method returns [`isr::R`](R) reader structure
405impl crate::Readable for ISRrs {}
406///`reset()` method sets ISR to value 0
407impl crate::Resettable for ISRrs {}
stm32f1/stm32f107/dma1/isr.rs

stm32f1/stm32f107/dma1/
isr.rs
