stm32f1/stm32f107/adc1/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**A/D converter ON / OFF
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ADON {
11    ///0: Disable ADC conversion/calibration and go to power down mode
12    Disabled = 0,
13    ///1: Enable ADC and to start conversion
14    Enabled = 1,
15}
16impl From<ADON> for bool {
17    #[inline(always)]
18    fn from(variant: ADON) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ADON` reader - A/D converter ON / OFF
23pub type ADON_R = crate::BitReader<ADON>;
24impl ADON_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ADON {
28        match self.bits {
29            false => ADON::Disabled,
30            true => ADON::Enabled,
31        }
32    }
33    ///Disable ADC conversion/calibration and go to power down mode
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ADON::Disabled
37    }
38    ///Enable ADC and to start conversion
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ADON::Enabled
42    }
43}
44///Field `ADON` writer - A/D converter ON / OFF
45pub type ADON_W<'a, REG> = crate::BitWriter<'a, REG, ADON>;
46impl<'a, REG> ADON_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Disable ADC conversion/calibration and go to power down mode
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(ADON::Disabled)
54    }
55    ///Enable ADC and to start conversion
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(ADON::Enabled)
59    }
60}
61/**Continuous conversion
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CONT {
67    ///0: Single conversion mode
68    Single = 0,
69    ///1: Continuous conversion mode
70    Continuous = 1,
71}
72impl From<CONT> for bool {
73    #[inline(always)]
74    fn from(variant: CONT) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CONT` reader - Continuous conversion
79pub type CONT_R = crate::BitReader<CONT>;
80impl CONT_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CONT {
84        match self.bits {
85            false => CONT::Single,
86            true => CONT::Continuous,
87        }
88    }
89    ///Single conversion mode
90    #[inline(always)]
91    pub fn is_single(&self) -> bool {
92        *self == CONT::Single
93    }
94    ///Continuous conversion mode
95    #[inline(always)]
96    pub fn is_continuous(&self) -> bool {
97        *self == CONT::Continuous
98    }
99}
100///Field `CONT` writer - Continuous conversion
101pub type CONT_W<'a, REG> = crate::BitWriter<'a, REG, CONT>;
102impl<'a, REG> CONT_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Single conversion mode
107    #[inline(always)]
108    pub fn single(self) -> &'a mut crate::W<REG> {
109        self.variant(CONT::Single)
110    }
111    ///Continuous conversion mode
112    #[inline(always)]
113    pub fn continuous(self) -> &'a mut crate::W<REG> {
114        self.variant(CONT::Continuous)
115    }
116}
117/**A/D calibration
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CALR {
123    ///0: Calibration completed
124    Complete = 0,
125    ///1: Calibrating
126    NotComplete = 1,
127}
128impl From<CALR> for bool {
129    #[inline(always)]
130    fn from(variant: CALR) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CAL` reader - A/D calibration
135pub type CAL_R = crate::BitReader<CALR>;
136impl CAL_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CALR {
140        match self.bits {
141            false => CALR::Complete,
142            true => CALR::NotComplete,
143        }
144    }
145    ///Calibration completed
146    #[inline(always)]
147    pub fn is_complete(&self) -> bool {
148        *self == CALR::Complete
149    }
150    ///Calibrating
151    #[inline(always)]
152    pub fn is_not_complete(&self) -> bool {
153        *self == CALR::NotComplete
154    }
155}
156/**A/D calibration
157
158Value on reset: 0*/
159#[cfg_attr(feature = "defmt", derive(defmt::Format))]
160#[derive(Clone, Copy, Debug, PartialEq, Eq)]
161pub enum CALW {
162    ///1: Enable calibration
163    Start = 1,
164}
165impl From<CALW> for bool {
166    #[inline(always)]
167    fn from(variant: CALW) -> Self {
168        variant as u8 != 0
169    }
170}
171///Field `CAL` writer - A/D calibration
172pub type CAL_W<'a, REG> = crate::BitWriter<'a, REG, CALW>;
173impl<'a, REG> CAL_W<'a, REG>
174where
175    REG: crate::Writable + crate::RegisterSpec,
176{
177    ///Enable calibration
178    #[inline(always)]
179    pub fn start(self) -> &'a mut crate::W<REG> {
180        self.variant(CALW::Start)
181    }
182}
183/**Reset calibration
184
185Value on reset: 0*/
186#[cfg_attr(feature = "defmt", derive(defmt::Format))]
187#[derive(Clone, Copy, Debug, PartialEq, Eq)]
188pub enum RSTCALR {
189    ///0: Calibration register initialized
190    Initialized = 0,
191    ///1: Initializing calibration register
192    NotInitialized = 1,
193}
194impl From<RSTCALR> for bool {
195    #[inline(always)]
196    fn from(variant: RSTCALR) -> Self {
197        variant as u8 != 0
198    }
199}
200///Field `RSTCAL` reader - Reset calibration
201pub type RSTCAL_R = crate::BitReader<RSTCALR>;
202impl RSTCAL_R {
203    ///Get enumerated values variant
204    #[inline(always)]
205    pub const fn variant(&self) -> RSTCALR {
206        match self.bits {
207            false => RSTCALR::Initialized,
208            true => RSTCALR::NotInitialized,
209        }
210    }
211    ///Calibration register initialized
212    #[inline(always)]
213    pub fn is_initialized(&self) -> bool {
214        *self == RSTCALR::Initialized
215    }
216    ///Initializing calibration register
217    #[inline(always)]
218    pub fn is_not_initialized(&self) -> bool {
219        *self == RSTCALR::NotInitialized
220    }
221}
222/**Reset calibration
223
224Value on reset: 0*/
225#[cfg_attr(feature = "defmt", derive(defmt::Format))]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum RSTCALW {
228    ///1: Initialize calibration register
229    Initialize = 1,
230}
231impl From<RSTCALW> for bool {
232    #[inline(always)]
233    fn from(variant: RSTCALW) -> Self {
234        variant as u8 != 0
235    }
236}
237///Field `RSTCAL` writer - Reset calibration
238pub type RSTCAL_W<'a, REG> = crate::BitWriter<'a, REG, RSTCALW>;
239impl<'a, REG> RSTCAL_W<'a, REG>
240where
241    REG: crate::Writable + crate::RegisterSpec,
242{
243    ///Initialize calibration register
244    #[inline(always)]
245    pub fn initialize(self) -> &'a mut crate::W<REG> {
246        self.variant(RSTCALW::Initialize)
247    }
248}
249/**Direct memory access mode
250
251Value on reset: 0*/
252#[cfg_attr(feature = "defmt", derive(defmt::Format))]
253#[derive(Clone, Copy, Debug, PartialEq, Eq)]
254pub enum DMA {
255    ///0: DMA mode disabled
256    Disabled = 0,
257    ///1: DMA mode enabled
258    Enabled = 1,
259}
260impl From<DMA> for bool {
261    #[inline(always)]
262    fn from(variant: DMA) -> Self {
263        variant as u8 != 0
264    }
265}
266///Field `DMA` reader - Direct memory access mode
267pub type DMA_R = crate::BitReader<DMA>;
268impl DMA_R {
269    ///Get enumerated values variant
270    #[inline(always)]
271    pub const fn variant(&self) -> DMA {
272        match self.bits {
273            false => DMA::Disabled,
274            true => DMA::Enabled,
275        }
276    }
277    ///DMA mode disabled
278    #[inline(always)]
279    pub fn is_disabled(&self) -> bool {
280        *self == DMA::Disabled
281    }
282    ///DMA mode enabled
283    #[inline(always)]
284    pub fn is_enabled(&self) -> bool {
285        *self == DMA::Enabled
286    }
287}
288///Field `DMA` writer - Direct memory access mode
289pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG, DMA>;
290impl<'a, REG> DMA_W<'a, REG>
291where
292    REG: crate::Writable + crate::RegisterSpec,
293{
294    ///DMA mode disabled
295    #[inline(always)]
296    pub fn disabled(self) -> &'a mut crate::W<REG> {
297        self.variant(DMA::Disabled)
298    }
299    ///DMA mode enabled
300    #[inline(always)]
301    pub fn enabled(self) -> &'a mut crate::W<REG> {
302        self.variant(DMA::Enabled)
303    }
304}
305/**Data alignment
306
307Value on reset: 0*/
308#[cfg_attr(feature = "defmt", derive(defmt::Format))]
309#[derive(Clone, Copy, Debug, PartialEq, Eq)]
310pub enum ALIGN {
311    ///0: Right Alignment
312    Right = 0,
313    ///1: Left Alignment
314    Left = 1,
315}
316impl From<ALIGN> for bool {
317    #[inline(always)]
318    fn from(variant: ALIGN) -> Self {
319        variant as u8 != 0
320    }
321}
322///Field `ALIGN` reader - Data alignment
323pub type ALIGN_R = crate::BitReader<ALIGN>;
324impl ALIGN_R {
325    ///Get enumerated values variant
326    #[inline(always)]
327    pub const fn variant(&self) -> ALIGN {
328        match self.bits {
329            false => ALIGN::Right,
330            true => ALIGN::Left,
331        }
332    }
333    ///Right Alignment
334    #[inline(always)]
335    pub fn is_right(&self) -> bool {
336        *self == ALIGN::Right
337    }
338    ///Left Alignment
339    #[inline(always)]
340    pub fn is_left(&self) -> bool {
341        *self == ALIGN::Left
342    }
343}
344///Field `ALIGN` writer - Data alignment
345pub type ALIGN_W<'a, REG> = crate::BitWriter<'a, REG, ALIGN>;
346impl<'a, REG> ALIGN_W<'a, REG>
347where
348    REG: crate::Writable + crate::RegisterSpec,
349{
350    ///Right Alignment
351    #[inline(always)]
352    pub fn right(self) -> &'a mut crate::W<REG> {
353        self.variant(ALIGN::Right)
354    }
355    ///Left Alignment
356    #[inline(always)]
357    pub fn left(self) -> &'a mut crate::W<REG> {
358        self.variant(ALIGN::Left)
359    }
360}
361/**External event select for injected group
362
363Value on reset: 0*/
364#[cfg_attr(feature = "defmt", derive(defmt::Format))]
365#[derive(Clone, Copy, Debug, PartialEq, Eq)]
366#[repr(u8)]
367pub enum JEXTSEL {
368    ///0: Timer 1 TRGO event
369    Tim1trgo = 0,
370    ///1: Timer 1 CC4 event
371    Tim1cc4 = 1,
372    ///2: Timer 2 TRGO event
373    Tim2trgo = 2,
374    ///3: Timer 2 CC1 event
375    Tim2cc1 = 3,
376    ///4: Timer 3 CC4 event
377    Tim3cc4 = 4,
378    ///5: Timer 4 TRGO event
379    Tim4trgo = 5,
380    ///6: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
381    Exti15 = 6,
382    ///7: JSWSTART
383    Jswstart = 7,
384}
385impl From<JEXTSEL> for u8 {
386    #[inline(always)]
387    fn from(variant: JEXTSEL) -> Self {
388        variant as _
389    }
390}
391impl crate::FieldSpec for JEXTSEL {
392    type Ux = u8;
393}
394impl crate::IsEnum for JEXTSEL {}
395///Field `JEXTSEL` reader - External event select for injected group
396pub type JEXTSEL_R = crate::FieldReader<JEXTSEL>;
397impl JEXTSEL_R {
398    ///Get enumerated values variant
399    #[inline(always)]
400    pub const fn variant(&self) -> JEXTSEL {
401        match self.bits {
402            0 => JEXTSEL::Tim1trgo,
403            1 => JEXTSEL::Tim1cc4,
404            2 => JEXTSEL::Tim2trgo,
405            3 => JEXTSEL::Tim2cc1,
406            4 => JEXTSEL::Tim3cc4,
407            5 => JEXTSEL::Tim4trgo,
408            6 => JEXTSEL::Exti15,
409            7 => JEXTSEL::Jswstart,
410            _ => unreachable!(),
411        }
412    }
413    ///Timer 1 TRGO event
414    #[inline(always)]
415    pub fn is_tim1trgo(&self) -> bool {
416        *self == JEXTSEL::Tim1trgo
417    }
418    ///Timer 1 CC4 event
419    #[inline(always)]
420    pub fn is_tim1cc4(&self) -> bool {
421        *self == JEXTSEL::Tim1cc4
422    }
423    ///Timer 2 TRGO event
424    #[inline(always)]
425    pub fn is_tim2trgo(&self) -> bool {
426        *self == JEXTSEL::Tim2trgo
427    }
428    ///Timer 2 CC1 event
429    #[inline(always)]
430    pub fn is_tim2cc1(&self) -> bool {
431        *self == JEXTSEL::Tim2cc1
432    }
433    ///Timer 3 CC4 event
434    #[inline(always)]
435    pub fn is_tim3cc4(&self) -> bool {
436        *self == JEXTSEL::Tim3cc4
437    }
438    ///Timer 4 TRGO event
439    #[inline(always)]
440    pub fn is_tim4trgo(&self) -> bool {
441        *self == JEXTSEL::Tim4trgo
442    }
443    ///EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
444    #[inline(always)]
445    pub fn is_exti15(&self) -> bool {
446        *self == JEXTSEL::Exti15
447    }
448    ///JSWSTART
449    #[inline(always)]
450    pub fn is_jswstart(&self) -> bool {
451        *self == JEXTSEL::Jswstart
452    }
453}
454///Field `JEXTSEL` writer - External event select for injected group
455pub type JEXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, JEXTSEL, crate::Safe>;
456impl<'a, REG> JEXTSEL_W<'a, REG>
457where
458    REG: crate::Writable + crate::RegisterSpec,
459    REG::Ux: From<u8>,
460{
461    ///Timer 1 TRGO event
462    #[inline(always)]
463    pub fn tim1trgo(self) -> &'a mut crate::W<REG> {
464        self.variant(JEXTSEL::Tim1trgo)
465    }
466    ///Timer 1 CC4 event
467    #[inline(always)]
468    pub fn tim1cc4(self) -> &'a mut crate::W<REG> {
469        self.variant(JEXTSEL::Tim1cc4)
470    }
471    ///Timer 2 TRGO event
472    #[inline(always)]
473    pub fn tim2trgo(self) -> &'a mut crate::W<REG> {
474        self.variant(JEXTSEL::Tim2trgo)
475    }
476    ///Timer 2 CC1 event
477    #[inline(always)]
478    pub fn tim2cc1(self) -> &'a mut crate::W<REG> {
479        self.variant(JEXTSEL::Tim2cc1)
480    }
481    ///Timer 3 CC4 event
482    #[inline(always)]
483    pub fn tim3cc4(self) -> &'a mut crate::W<REG> {
484        self.variant(JEXTSEL::Tim3cc4)
485    }
486    ///Timer 4 TRGO event
487    #[inline(always)]
488    pub fn tim4trgo(self) -> &'a mut crate::W<REG> {
489        self.variant(JEXTSEL::Tim4trgo)
490    }
491    ///EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
492    #[inline(always)]
493    pub fn exti15(self) -> &'a mut crate::W<REG> {
494        self.variant(JEXTSEL::Exti15)
495    }
496    ///JSWSTART
497    #[inline(always)]
498    pub fn jswstart(self) -> &'a mut crate::W<REG> {
499        self.variant(JEXTSEL::Jswstart)
500    }
501}
502/**External trigger conversion mode for injected channels
503
504Value on reset: 0*/
505#[cfg_attr(feature = "defmt", derive(defmt::Format))]
506#[derive(Clone, Copy, Debug, PartialEq, Eq)]
507pub enum JEXTTRIG {
508    ///0: Conversion on external event disabled
509    Disabled = 0,
510    ///1: Conversion on external event enabled
511    Enabled = 1,
512}
513impl From<JEXTTRIG> for bool {
514    #[inline(always)]
515    fn from(variant: JEXTTRIG) -> Self {
516        variant as u8 != 0
517    }
518}
519///Field `JEXTTRIG` reader - External trigger conversion mode for injected channels
520pub type JEXTTRIG_R = crate::BitReader<JEXTTRIG>;
521impl JEXTTRIG_R {
522    ///Get enumerated values variant
523    #[inline(always)]
524    pub const fn variant(&self) -> JEXTTRIG {
525        match self.bits {
526            false => JEXTTRIG::Disabled,
527            true => JEXTTRIG::Enabled,
528        }
529    }
530    ///Conversion on external event disabled
531    #[inline(always)]
532    pub fn is_disabled(&self) -> bool {
533        *self == JEXTTRIG::Disabled
534    }
535    ///Conversion on external event enabled
536    #[inline(always)]
537    pub fn is_enabled(&self) -> bool {
538        *self == JEXTTRIG::Enabled
539    }
540}
541///Field `JEXTTRIG` writer - External trigger conversion mode for injected channels
542pub type JEXTTRIG_W<'a, REG> = crate::BitWriter<'a, REG, JEXTTRIG>;
543impl<'a, REG> JEXTTRIG_W<'a, REG>
544where
545    REG: crate::Writable + crate::RegisterSpec,
546{
547    ///Conversion on external event disabled
548    #[inline(always)]
549    pub fn disabled(self) -> &'a mut crate::W<REG> {
550        self.variant(JEXTTRIG::Disabled)
551    }
552    ///Conversion on external event enabled
553    #[inline(always)]
554    pub fn enabled(self) -> &'a mut crate::W<REG> {
555        self.variant(JEXTTRIG::Enabled)
556    }
557}
558/**External event select for regular group
559
560Value on reset: 0*/
561#[cfg_attr(feature = "defmt", derive(defmt::Format))]
562#[derive(Clone, Copy, Debug, PartialEq, Eq)]
563#[repr(u8)]
564pub enum EXTSEL {
565    ///0: Timer 1 CC1 event
566    Tim1cc1 = 0,
567    ///1: Timer 1 CC2 event
568    Tim1cc2 = 1,
569    ///2: Timer 1 CC3 event
570    Tim1cc3 = 2,
571    ///3: Timer 2 CC2 event
572    Tim2cc2 = 3,
573    ///4: Timer 3 TRGO event
574    Tim3trgo = 4,
575    ///5: Timer 4 CC4 event
576    Tim4cc4 = 5,
577    ///6: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
578    Exti11 = 6,
579    ///7: SWSTART
580    Swstart = 7,
581}
582impl From<EXTSEL> for u8 {
583    #[inline(always)]
584    fn from(variant: EXTSEL) -> Self {
585        variant as _
586    }
587}
588impl crate::FieldSpec for EXTSEL {
589    type Ux = u8;
590}
591impl crate::IsEnum for EXTSEL {}
592///Field `EXTSEL` reader - External event select for regular group
593pub type EXTSEL_R = crate::FieldReader<EXTSEL>;
594impl EXTSEL_R {
595    ///Get enumerated values variant
596    #[inline(always)]
597    pub const fn variant(&self) -> EXTSEL {
598        match self.bits {
599            0 => EXTSEL::Tim1cc1,
600            1 => EXTSEL::Tim1cc2,
601            2 => EXTSEL::Tim1cc3,
602            3 => EXTSEL::Tim2cc2,
603            4 => EXTSEL::Tim3trgo,
604            5 => EXTSEL::Tim4cc4,
605            6 => EXTSEL::Exti11,
606            7 => EXTSEL::Swstart,
607            _ => unreachable!(),
608        }
609    }
610    ///Timer 1 CC1 event
611    #[inline(always)]
612    pub fn is_tim1cc1(&self) -> bool {
613        *self == EXTSEL::Tim1cc1
614    }
615    ///Timer 1 CC2 event
616    #[inline(always)]
617    pub fn is_tim1cc2(&self) -> bool {
618        *self == EXTSEL::Tim1cc2
619    }
620    ///Timer 1 CC3 event
621    #[inline(always)]
622    pub fn is_tim1cc3(&self) -> bool {
623        *self == EXTSEL::Tim1cc3
624    }
625    ///Timer 2 CC2 event
626    #[inline(always)]
627    pub fn is_tim2cc2(&self) -> bool {
628        *self == EXTSEL::Tim2cc2
629    }
630    ///Timer 3 TRGO event
631    #[inline(always)]
632    pub fn is_tim3trgo(&self) -> bool {
633        *self == EXTSEL::Tim3trgo
634    }
635    ///Timer 4 CC4 event
636    #[inline(always)]
637    pub fn is_tim4cc4(&self) -> bool {
638        *self == EXTSEL::Tim4cc4
639    }
640    ///EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
641    #[inline(always)]
642    pub fn is_exti11(&self) -> bool {
643        *self == EXTSEL::Exti11
644    }
645    ///SWSTART
646    #[inline(always)]
647    pub fn is_swstart(&self) -> bool {
648        *self == EXTSEL::Swstart
649    }
650}
651///Field `EXTSEL` writer - External event select for regular group
652pub type EXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, EXTSEL, crate::Safe>;
653impl<'a, REG> EXTSEL_W<'a, REG>
654where
655    REG: crate::Writable + crate::RegisterSpec,
656    REG::Ux: From<u8>,
657{
658    ///Timer 1 CC1 event
659    #[inline(always)]
660    pub fn tim1cc1(self) -> &'a mut crate::W<REG> {
661        self.variant(EXTSEL::Tim1cc1)
662    }
663    ///Timer 1 CC2 event
664    #[inline(always)]
665    pub fn tim1cc2(self) -> &'a mut crate::W<REG> {
666        self.variant(EXTSEL::Tim1cc2)
667    }
668    ///Timer 1 CC3 event
669    #[inline(always)]
670    pub fn tim1cc3(self) -> &'a mut crate::W<REG> {
671        self.variant(EXTSEL::Tim1cc3)
672    }
673    ///Timer 2 CC2 event
674    #[inline(always)]
675    pub fn tim2cc2(self) -> &'a mut crate::W<REG> {
676        self.variant(EXTSEL::Tim2cc2)
677    }
678    ///Timer 3 TRGO event
679    #[inline(always)]
680    pub fn tim3trgo(self) -> &'a mut crate::W<REG> {
681        self.variant(EXTSEL::Tim3trgo)
682    }
683    ///Timer 4 CC4 event
684    #[inline(always)]
685    pub fn tim4cc4(self) -> &'a mut crate::W<REG> {
686        self.variant(EXTSEL::Tim4cc4)
687    }
688    ///EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
689    #[inline(always)]
690    pub fn exti11(self) -> &'a mut crate::W<REG> {
691        self.variant(EXTSEL::Exti11)
692    }
693    ///SWSTART
694    #[inline(always)]
695    pub fn swstart(self) -> &'a mut crate::W<REG> {
696        self.variant(EXTSEL::Swstart)
697    }
698}
699/**External trigger conversion mode for regular channels
700
701Value on reset: 0*/
702#[cfg_attr(feature = "defmt", derive(defmt::Format))]
703#[derive(Clone, Copy, Debug, PartialEq, Eq)]
704pub enum EXTTRIG {
705    ///0: Conversion on external event disabled
706    Disabled = 0,
707    ///1: Conversion on external event enabled
708    Enabled = 1,
709}
710impl From<EXTTRIG> for bool {
711    #[inline(always)]
712    fn from(variant: EXTTRIG) -> Self {
713        variant as u8 != 0
714    }
715}
716///Field `EXTTRIG` reader - External trigger conversion mode for regular channels
717pub type EXTTRIG_R = crate::BitReader<EXTTRIG>;
718impl EXTTRIG_R {
719    ///Get enumerated values variant
720    #[inline(always)]
721    pub const fn variant(&self) -> EXTTRIG {
722        match self.bits {
723            false => EXTTRIG::Disabled,
724            true => EXTTRIG::Enabled,
725        }
726    }
727    ///Conversion on external event disabled
728    #[inline(always)]
729    pub fn is_disabled(&self) -> bool {
730        *self == EXTTRIG::Disabled
731    }
732    ///Conversion on external event enabled
733    #[inline(always)]
734    pub fn is_enabled(&self) -> bool {
735        *self == EXTTRIG::Enabled
736    }
737}
738///Field `EXTTRIG` writer - External trigger conversion mode for regular channels
739pub type EXTTRIG_W<'a, REG> = crate::BitWriter<'a, REG, EXTTRIG>;
740impl<'a, REG> EXTTRIG_W<'a, REG>
741where
742    REG: crate::Writable + crate::RegisterSpec,
743{
744    ///Conversion on external event disabled
745    #[inline(always)]
746    pub fn disabled(self) -> &'a mut crate::W<REG> {
747        self.variant(EXTTRIG::Disabled)
748    }
749    ///Conversion on external event enabled
750    #[inline(always)]
751    pub fn enabled(self) -> &'a mut crate::W<REG> {
752        self.variant(EXTTRIG::Enabled)
753    }
754}
755/**Start conversion of injected channels
756
757Value on reset: 0*/
758#[cfg_attr(feature = "defmt", derive(defmt::Format))]
759#[derive(Clone, Copy, Debug, PartialEq, Eq)]
760pub enum JSWSTARTR {
761    ///0: Reset state
762    Started = 0,
763    ///1: Starting conversion of injected channels
764    NotStarted = 1,
765}
766impl From<JSWSTARTR> for bool {
767    #[inline(always)]
768    fn from(variant: JSWSTARTR) -> Self {
769        variant as u8 != 0
770    }
771}
772///Field `JSWSTART` reader - Start conversion of injected channels
773pub type JSWSTART_R = crate::BitReader<JSWSTARTR>;
774impl JSWSTART_R {
775    ///Get enumerated values variant
776    #[inline(always)]
777    pub const fn variant(&self) -> JSWSTARTR {
778        match self.bits {
779            false => JSWSTARTR::Started,
780            true => JSWSTARTR::NotStarted,
781        }
782    }
783    ///Reset state
784    #[inline(always)]
785    pub fn is_started(&self) -> bool {
786        *self == JSWSTARTR::Started
787    }
788    ///Starting conversion of injected channels
789    #[inline(always)]
790    pub fn is_not_started(&self) -> bool {
791        *self == JSWSTARTR::NotStarted
792    }
793}
794/**Start conversion of injected channels
795
796Value on reset: 0*/
797#[cfg_attr(feature = "defmt", derive(defmt::Format))]
798#[derive(Clone, Copy, Debug, PartialEq, Eq)]
799pub enum JSWSTARTW {
800    ///1: Start conversion of injected channels
801    Start = 1,
802}
803impl From<JSWSTARTW> for bool {
804    #[inline(always)]
805    fn from(variant: JSWSTARTW) -> Self {
806        variant as u8 != 0
807    }
808}
809///Field `JSWSTART` writer - Start conversion of injected channels
810pub type JSWSTART_W<'a, REG> = crate::BitWriter<'a, REG, JSWSTARTW>;
811impl<'a, REG> JSWSTART_W<'a, REG>
812where
813    REG: crate::Writable + crate::RegisterSpec,
814{
815    ///Start conversion of injected channels
816    #[inline(always)]
817    pub fn start(self) -> &'a mut crate::W<REG> {
818        self.variant(JSWSTARTW::Start)
819    }
820}
821/**Start conversion of regular channels
822
823Value on reset: 0*/
824#[cfg_attr(feature = "defmt", derive(defmt::Format))]
825#[derive(Clone, Copy, Debug, PartialEq, Eq)]
826pub enum SWSTARTR {
827    ///0: Reset state
828    Started = 0,
829    ///1: Starting conversion of regular channels
830    NotStarted = 1,
831}
832impl From<SWSTARTR> for bool {
833    #[inline(always)]
834    fn from(variant: SWSTARTR) -> Self {
835        variant as u8 != 0
836    }
837}
838///Field `SWSTART` reader - Start conversion of regular channels
839pub type SWSTART_R = crate::BitReader<SWSTARTR>;
840impl SWSTART_R {
841    ///Get enumerated values variant
842    #[inline(always)]
843    pub const fn variant(&self) -> SWSTARTR {
844        match self.bits {
845            false => SWSTARTR::Started,
846            true => SWSTARTR::NotStarted,
847        }
848    }
849    ///Reset state
850    #[inline(always)]
851    pub fn is_started(&self) -> bool {
852        *self == SWSTARTR::Started
853    }
854    ///Starting conversion of regular channels
855    #[inline(always)]
856    pub fn is_not_started(&self) -> bool {
857        *self == SWSTARTR::NotStarted
858    }
859}
860/**Start conversion of regular channels
861
862Value on reset: 0*/
863#[cfg_attr(feature = "defmt", derive(defmt::Format))]
864#[derive(Clone, Copy, Debug, PartialEq, Eq)]
865pub enum SWSTARTW {
866    ///1: Start conversion of regular channels
867    Start = 1,
868}
869impl From<SWSTARTW> for bool {
870    #[inline(always)]
871    fn from(variant: SWSTARTW) -> Self {
872        variant as u8 != 0
873    }
874}
875///Field `SWSTART` writer - Start conversion of regular channels
876pub type SWSTART_W<'a, REG> = crate::BitWriter<'a, REG, SWSTARTW>;
877impl<'a, REG> SWSTART_W<'a, REG>
878where
879    REG: crate::Writable + crate::RegisterSpec,
880{
881    ///Start conversion of regular channels
882    #[inline(always)]
883    pub fn start(self) -> &'a mut crate::W<REG> {
884        self.variant(SWSTARTW::Start)
885    }
886}
887/**Temperature sensor and VREFINT enable
888
889Value on reset: 0*/
890#[cfg_attr(feature = "defmt", derive(defmt::Format))]
891#[derive(Clone, Copy, Debug, PartialEq, Eq)]
892pub enum TSVREFE {
893    ///0: Temperature sensor and V_REFINT channel disabled
894    Disabled = 0,
895    ///1: Temperature sensor and V_REFINT channel enabled
896    Enabled = 1,
897}
898impl From<TSVREFE> for bool {
899    #[inline(always)]
900    fn from(variant: TSVREFE) -> Self {
901        variant as u8 != 0
902    }
903}
904///Field `TSVREFE` reader - Temperature sensor and VREFINT enable
905pub type TSVREFE_R = crate::BitReader<TSVREFE>;
906impl TSVREFE_R {
907    ///Get enumerated values variant
908    #[inline(always)]
909    pub const fn variant(&self) -> TSVREFE {
910        match self.bits {
911            false => TSVREFE::Disabled,
912            true => TSVREFE::Enabled,
913        }
914    }
915    ///Temperature sensor and V_REFINT channel disabled
916    #[inline(always)]
917    pub fn is_disabled(&self) -> bool {
918        *self == TSVREFE::Disabled
919    }
920    ///Temperature sensor and V_REFINT channel enabled
921    #[inline(always)]
922    pub fn is_enabled(&self) -> bool {
923        *self == TSVREFE::Enabled
924    }
925}
926///Field `TSVREFE` writer - Temperature sensor and VREFINT enable
927pub type TSVREFE_W<'a, REG> = crate::BitWriter<'a, REG, TSVREFE>;
928impl<'a, REG> TSVREFE_W<'a, REG>
929where
930    REG: crate::Writable + crate::RegisterSpec,
931{
932    ///Temperature sensor and V_REFINT channel disabled
933    #[inline(always)]
934    pub fn disabled(self) -> &'a mut crate::W<REG> {
935        self.variant(TSVREFE::Disabled)
936    }
937    ///Temperature sensor and V_REFINT channel enabled
938    #[inline(always)]
939    pub fn enabled(self) -> &'a mut crate::W<REG> {
940        self.variant(TSVREFE::Enabled)
941    }
942}
943impl R {
944    ///Bit 0 - A/D converter ON / OFF
945    #[inline(always)]
946    pub fn adon(&self) -> ADON_R {
947        ADON_R::new((self.bits & 1) != 0)
948    }
949    ///Bit 1 - Continuous conversion
950    #[inline(always)]
951    pub fn cont(&self) -> CONT_R {
952        CONT_R::new(((self.bits >> 1) & 1) != 0)
953    }
954    ///Bit 2 - A/D calibration
955    #[inline(always)]
956    pub fn cal(&self) -> CAL_R {
957        CAL_R::new(((self.bits >> 2) & 1) != 0)
958    }
959    ///Bit 3 - Reset calibration
960    #[inline(always)]
961    pub fn rstcal(&self) -> RSTCAL_R {
962        RSTCAL_R::new(((self.bits >> 3) & 1) != 0)
963    }
964    ///Bit 8 - Direct memory access mode
965    #[inline(always)]
966    pub fn dma(&self) -> DMA_R {
967        DMA_R::new(((self.bits >> 8) & 1) != 0)
968    }
969    ///Bit 11 - Data alignment
970    #[inline(always)]
971    pub fn align(&self) -> ALIGN_R {
972        ALIGN_R::new(((self.bits >> 11) & 1) != 0)
973    }
974    ///Bits 12:14 - External event select for injected group
975    #[inline(always)]
976    pub fn jextsel(&self) -> JEXTSEL_R {
977        JEXTSEL_R::new(((self.bits >> 12) & 7) as u8)
978    }
979    ///Bit 15 - External trigger conversion mode for injected channels
980    #[inline(always)]
981    pub fn jexttrig(&self) -> JEXTTRIG_R {
982        JEXTTRIG_R::new(((self.bits >> 15) & 1) != 0)
983    }
984    ///Bits 17:19 - External event select for regular group
985    #[inline(always)]
986    pub fn extsel(&self) -> EXTSEL_R {
987        EXTSEL_R::new(((self.bits >> 17) & 7) as u8)
988    }
989    ///Bit 20 - External trigger conversion mode for regular channels
990    #[inline(always)]
991    pub fn exttrig(&self) -> EXTTRIG_R {
992        EXTTRIG_R::new(((self.bits >> 20) & 1) != 0)
993    }
994    ///Bit 21 - Start conversion of injected channels
995    #[inline(always)]
996    pub fn jswstart(&self) -> JSWSTART_R {
997        JSWSTART_R::new(((self.bits >> 21) & 1) != 0)
998    }
999    ///Bit 22 - Start conversion of regular channels
1000    #[inline(always)]
1001    pub fn swstart(&self) -> SWSTART_R {
1002        SWSTART_R::new(((self.bits >> 22) & 1) != 0)
1003    }
1004    ///Bit 23 - Temperature sensor and VREFINT enable
1005    #[inline(always)]
1006    pub fn tsvrefe(&self) -> TSVREFE_R {
1007        TSVREFE_R::new(((self.bits >> 23) & 1) != 0)
1008    }
1009}
1010impl core::fmt::Debug for R {
1011    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1012        f.debug_struct("CR2")
1013            .field("tsvrefe", &self.tsvrefe())
1014            .field("swstart", &self.swstart())
1015            .field("jswstart", &self.jswstart())
1016            .field("exttrig", &self.exttrig())
1017            .field("extsel", &self.extsel())
1018            .field("jexttrig", &self.jexttrig())
1019            .field("jextsel", &self.jextsel())
1020            .field("align", &self.align())
1021            .field("dma", &self.dma())
1022            .field("rstcal", &self.rstcal())
1023            .field("cal", &self.cal())
1024            .field("cont", &self.cont())
1025            .field("adon", &self.adon())
1026            .finish()
1027    }
1028}
1029impl W {
1030    ///Bit 0 - A/D converter ON / OFF
1031    #[inline(always)]
1032    pub fn adon(&mut self) -> ADON_W<CR2rs> {
1033        ADON_W::new(self, 0)
1034    }
1035    ///Bit 1 - Continuous conversion
1036    #[inline(always)]
1037    pub fn cont(&mut self) -> CONT_W<CR2rs> {
1038        CONT_W::new(self, 1)
1039    }
1040    ///Bit 2 - A/D calibration
1041    #[inline(always)]
1042    pub fn cal(&mut self) -> CAL_W<CR2rs> {
1043        CAL_W::new(self, 2)
1044    }
1045    ///Bit 3 - Reset calibration
1046    #[inline(always)]
1047    pub fn rstcal(&mut self) -> RSTCAL_W<CR2rs> {
1048        RSTCAL_W::new(self, 3)
1049    }
1050    ///Bit 8 - Direct memory access mode
1051    #[inline(always)]
1052    pub fn dma(&mut self) -> DMA_W<CR2rs> {
1053        DMA_W::new(self, 8)
1054    }
1055    ///Bit 11 - Data alignment
1056    #[inline(always)]
1057    pub fn align(&mut self) -> ALIGN_W<CR2rs> {
1058        ALIGN_W::new(self, 11)
1059    }
1060    ///Bits 12:14 - External event select for injected group
1061    #[inline(always)]
1062    pub fn jextsel(&mut self) -> JEXTSEL_W<CR2rs> {
1063        JEXTSEL_W::new(self, 12)
1064    }
1065    ///Bit 15 - External trigger conversion mode for injected channels
1066    #[inline(always)]
1067    pub fn jexttrig(&mut self) -> JEXTTRIG_W<CR2rs> {
1068        JEXTTRIG_W::new(self, 15)
1069    }
1070    ///Bits 17:19 - External event select for regular group
1071    #[inline(always)]
1072    pub fn extsel(&mut self) -> EXTSEL_W<CR2rs> {
1073        EXTSEL_W::new(self, 17)
1074    }
1075    ///Bit 20 - External trigger conversion mode for regular channels
1076    #[inline(always)]
1077    pub fn exttrig(&mut self) -> EXTTRIG_W<CR2rs> {
1078        EXTTRIG_W::new(self, 20)
1079    }
1080    ///Bit 21 - Start conversion of injected channels
1081    #[inline(always)]
1082    pub fn jswstart(&mut self) -> JSWSTART_W<CR2rs> {
1083        JSWSTART_W::new(self, 21)
1084    }
1085    ///Bit 22 - Start conversion of regular channels
1086    #[inline(always)]
1087    pub fn swstart(&mut self) -> SWSTART_W<CR2rs> {
1088        SWSTART_W::new(self, 22)
1089    }
1090    ///Bit 23 - Temperature sensor and VREFINT enable
1091    #[inline(always)]
1092    pub fn tsvrefe(&mut self) -> TSVREFE_W<CR2rs> {
1093        TSVREFE_W::new(self, 23)
1094    }
1095}
1096/**control register 2
1097
1098You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1099
1100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC1:CR2)*/
1101pub struct CR2rs;
1102impl crate::RegisterSpec for CR2rs {
1103    type Ux = u32;
1104}
1105///`read()` method returns [`cr2::R`](R) reader structure
1106impl crate::Readable for CR2rs {}
1107///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
1108impl crate::Writable for CR2rs {
1109    type Safety = crate::Unsafe;
1110}
1111///`reset()` method sets CR2 to value 0
1112impl crate::Resettable for CR2rs {}
stm32f1/stm32f107/adc1/cr2.rs

stm32f1/stm32f107/adc1/
cr2.rs
