stm32f1/stm32f103/tim6/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Update interrupt flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIFR {
11    ///0: No update occurred
12    NoUpdateOccurred = 0,
13    ///1: Update interrupt pending
14    UpdatePending = 1,
15}
16impl From<UIFR> for bool {
17    #[inline(always)]
18    fn from(variant: UIFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIF` reader - Update interrupt flag
23pub type UIF_R = crate::BitReader<UIFR>;
24impl UIF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIFR {
28        match self.bits {
29            false => UIFR::NoUpdateOccurred,
30            true => UIFR::UpdatePending,
31        }
32    }
33    ///No update occurred
34    #[inline(always)]
35    pub fn is_no_update_occurred(&self) -> bool {
36        *self == UIFR::NoUpdateOccurred
37    }
38    ///Update interrupt pending
39    #[inline(always)]
40    pub fn is_update_pending(&self) -> bool {
41        *self == UIFR::UpdatePending
42    }
43}
44/**Update interrupt flag
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum UIFW {
50    ///0: Clear flag
51    Clear = 0,
52}
53impl From<UIFW> for bool {
54    #[inline(always)]
55    fn from(variant: UIFW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `UIF` writer - Update interrupt flag
60pub type UIF_W<'a, REG> = crate::BitWriter0C<'a, REG, UIFW>;
61impl<'a, REG> UIF_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(UIFW::Clear)
69    }
70}
71impl R {
72    ///Bit 0 - Update interrupt flag
73    #[inline(always)]
74    pub fn uif(&self) -> UIF_R {
75        UIF_R::new((self.bits & 1) != 0)
76    }
77}
78impl core::fmt::Debug for R {
79    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
80        f.debug_struct("SR").field("uif", &self.uif()).finish()
81    }
82}
83impl W {
84    ///Bit 0 - Update interrupt flag
85    #[inline(always)]
86    pub fn uif(&mut self) -> UIF_W<SRrs> {
87        UIF_W::new(self, 0)
88    }
89}
90/**status register
91
92You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM6:SR)*/
95pub struct SRrs;
96impl crate::RegisterSpec for SRrs {
97    type Ux = u32;
98}
99///`read()` method returns [`sr::R`](R) reader structure
100impl crate::Readable for SRrs {}
101///`write(|w| ..)` method takes [`sr::W`](W) writer structure
102impl crate::Writable for SRrs {
103    type Safety = crate::Unsafe;
104    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01;
105}
106///`reset()` method sets SR to value 0
107impl crate::Resettable for SRrs {}
stm32f1/stm32f103/tim6/sr.rs

stm32f1/stm32f103/tim6/
sr.rs
