stm32f1/stm32f103/rcc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Internal High Speed clock enable
6
7Value on reset: 1*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum HSION {
11    ///0: Clock Off
12    Off = 0,
13    ///1: Clock On
14    On = 1,
15}
16impl From<HSION> for bool {
17    #[inline(always)]
18    fn from(variant: HSION) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `HSION` reader - Internal High Speed clock enable
23pub type HSION_R = crate::BitReader<HSION>;
24impl HSION_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> HSION {
28        match self.bits {
29            false => HSION::Off,
30            true => HSION::On,
31        }
32    }
33    ///Clock Off
34    #[inline(always)]
35    pub fn is_off(&self) -> bool {
36        *self == HSION::Off
37    }
38    ///Clock On
39    #[inline(always)]
40    pub fn is_on(&self) -> bool {
41        *self == HSION::On
42    }
43}
44///Field `HSION` writer - Internal High Speed clock enable
45pub type HSION_W<'a, REG> = crate::BitWriter<'a, REG, HSION>;
46impl<'a, REG> HSION_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Clock Off
51    #[inline(always)]
52    pub fn off(self) -> &'a mut crate::W<REG> {
53        self.variant(HSION::Off)
54    }
55    ///Clock On
56    #[inline(always)]
57    pub fn on(self) -> &'a mut crate::W<REG> {
58        self.variant(HSION::On)
59    }
60}
61/**Internal High Speed clock ready flag
62
63Value on reset: 1*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum HSIRDYR {
67    ///0: Clock not ready
68    NotReady = 0,
69    ///1: Clock ready
70    Ready = 1,
71}
72impl From<HSIRDYR> for bool {
73    #[inline(always)]
74    fn from(variant: HSIRDYR) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `HSIRDY` reader - Internal High Speed clock ready flag
79pub type HSIRDY_R = crate::BitReader<HSIRDYR>;
80impl HSIRDY_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> HSIRDYR {
84        match self.bits {
85            false => HSIRDYR::NotReady,
86            true => HSIRDYR::Ready,
87        }
88    }
89    ///Clock not ready
90    #[inline(always)]
91    pub fn is_not_ready(&self) -> bool {
92        *self == HSIRDYR::NotReady
93    }
94    ///Clock ready
95    #[inline(always)]
96    pub fn is_ready(&self) -> bool {
97        *self == HSIRDYR::Ready
98    }
99}
100///Field `HSITRIM` reader - Internal High Speed clock trimming
101pub type HSITRIM_R = crate::FieldReader;
102///Field `HSITRIM` writer - Internal High Speed clock trimming
103pub type HSITRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
104///Field `HSICAL` reader - Internal High Speed clock Calibration
105pub type HSICAL_R = crate::FieldReader;
106///Field `HSEON` reader - External High Speed clock enable
107pub use HSION_R as HSEON_R;
108///Field `HSEON` writer - External High Speed clock enable
109pub use HSION_W as HSEON_W;
110///Field `HSERDY` reader - External High Speed clock ready flag
111pub use HSIRDY_R as HSERDY_R;
112/**External High Speed clock Bypass
113
114Value on reset: 0*/
115#[cfg_attr(feature = "defmt", derive(defmt::Format))]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum HSEBYP {
118    ///0: HSE crystal oscillator not bypassed
119    NotBypassed = 0,
120    ///1: HSE crystal oscillator bypassed with external clock
121    Bypassed = 1,
122}
123impl From<HSEBYP> for bool {
124    #[inline(always)]
125    fn from(variant: HSEBYP) -> Self {
126        variant as u8 != 0
127    }
128}
129///Field `HSEBYP` reader - External High Speed clock Bypass
130pub type HSEBYP_R = crate::BitReader<HSEBYP>;
131impl HSEBYP_R {
132    ///Get enumerated values variant
133    #[inline(always)]
134    pub const fn variant(&self) -> HSEBYP {
135        match self.bits {
136            false => HSEBYP::NotBypassed,
137            true => HSEBYP::Bypassed,
138        }
139    }
140    ///HSE crystal oscillator not bypassed
141    #[inline(always)]
142    pub fn is_not_bypassed(&self) -> bool {
143        *self == HSEBYP::NotBypassed
144    }
145    ///HSE crystal oscillator bypassed with external clock
146    #[inline(always)]
147    pub fn is_bypassed(&self) -> bool {
148        *self == HSEBYP::Bypassed
149    }
150}
151///Field `HSEBYP` writer - External High Speed clock Bypass
152pub type HSEBYP_W<'a, REG> = crate::BitWriter<'a, REG, HSEBYP>;
153impl<'a, REG> HSEBYP_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    ///HSE crystal oscillator not bypassed
158    #[inline(always)]
159    pub fn not_bypassed(self) -> &'a mut crate::W<REG> {
160        self.variant(HSEBYP::NotBypassed)
161    }
162    ///HSE crystal oscillator bypassed with external clock
163    #[inline(always)]
164    pub fn bypassed(self) -> &'a mut crate::W<REG> {
165        self.variant(HSEBYP::Bypassed)
166    }
167}
168/**Clock Security System enable
169
170Value on reset: 0*/
171#[cfg_attr(feature = "defmt", derive(defmt::Format))]
172#[derive(Clone, Copy, Debug, PartialEq, Eq)]
173pub enum CSSON {
174    ///0: Clock security system disabled (clock detector OFF)
175    Off = 0,
176    ///1: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
177    On = 1,
178}
179impl From<CSSON> for bool {
180    #[inline(always)]
181    fn from(variant: CSSON) -> Self {
182        variant as u8 != 0
183    }
184}
185///Field `CSSON` reader - Clock Security System enable
186pub type CSSON_R = crate::BitReader<CSSON>;
187impl CSSON_R {
188    ///Get enumerated values variant
189    #[inline(always)]
190    pub const fn variant(&self) -> CSSON {
191        match self.bits {
192            false => CSSON::Off,
193            true => CSSON::On,
194        }
195    }
196    ///Clock security system disabled (clock detector OFF)
197    #[inline(always)]
198    pub fn is_off(&self) -> bool {
199        *self == CSSON::Off
200    }
201    ///Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
202    #[inline(always)]
203    pub fn is_on(&self) -> bool {
204        *self == CSSON::On
205    }
206}
207///Field `CSSON` writer - Clock Security System enable
208pub type CSSON_W<'a, REG> = crate::BitWriter<'a, REG, CSSON>;
209impl<'a, REG> CSSON_W<'a, REG>
210where
211    REG: crate::Writable + crate::RegisterSpec,
212{
213    ///Clock security system disabled (clock detector OFF)
214    #[inline(always)]
215    pub fn off(self) -> &'a mut crate::W<REG> {
216        self.variant(CSSON::Off)
217    }
218    ///Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
219    #[inline(always)]
220    pub fn on(self) -> &'a mut crate::W<REG> {
221        self.variant(CSSON::On)
222    }
223}
224///Field `PLLON` reader - PLL enable
225pub use HSION_R as PLLON_R;
226///Field `PLLON` writer - PLL enable
227pub use HSION_W as PLLON_W;
228///Field `PLLRDY` reader - PLL clock ready flag
229pub use HSIRDY_R as PLLRDY_R;
230impl R {
231    ///Bit 0 - Internal High Speed clock enable
232    #[inline(always)]
233    pub fn hsion(&self) -> HSION_R {
234        HSION_R::new((self.bits & 1) != 0)
235    }
236    ///Bit 1 - Internal High Speed clock ready flag
237    #[inline(always)]
238    pub fn hsirdy(&self) -> HSIRDY_R {
239        HSIRDY_R::new(((self.bits >> 1) & 1) != 0)
240    }
241    ///Bits 3:7 - Internal High Speed clock trimming
242    #[inline(always)]
243    pub fn hsitrim(&self) -> HSITRIM_R {
244        HSITRIM_R::new(((self.bits >> 3) & 0x1f) as u8)
245    }
246    ///Bits 8:15 - Internal High Speed clock Calibration
247    #[inline(always)]
248    pub fn hsical(&self) -> HSICAL_R {
249        HSICAL_R::new(((self.bits >> 8) & 0xff) as u8)
250    }
251    ///Bit 16 - External High Speed clock enable
252    #[inline(always)]
253    pub fn hseon(&self) -> HSEON_R {
254        HSEON_R::new(((self.bits >> 16) & 1) != 0)
255    }
256    ///Bit 17 - External High Speed clock ready flag
257    #[inline(always)]
258    pub fn hserdy(&self) -> HSERDY_R {
259        HSERDY_R::new(((self.bits >> 17) & 1) != 0)
260    }
261    ///Bit 18 - External High Speed clock Bypass
262    #[inline(always)]
263    pub fn hsebyp(&self) -> HSEBYP_R {
264        HSEBYP_R::new(((self.bits >> 18) & 1) != 0)
265    }
266    ///Bit 19 - Clock Security System enable
267    #[inline(always)]
268    pub fn csson(&self) -> CSSON_R {
269        CSSON_R::new(((self.bits >> 19) & 1) != 0)
270    }
271    ///Bit 24 - PLL enable
272    #[inline(always)]
273    pub fn pllon(&self) -> PLLON_R {
274        PLLON_R::new(((self.bits >> 24) & 1) != 0)
275    }
276    ///Bit 25 - PLL clock ready flag
277    #[inline(always)]
278    pub fn pllrdy(&self) -> PLLRDY_R {
279        PLLRDY_R::new(((self.bits >> 25) & 1) != 0)
280    }
281}
282impl core::fmt::Debug for R {
283    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
284        f.debug_struct("CR")
285            .field("hsion", &self.hsion())
286            .field("hsirdy", &self.hsirdy())
287            .field("hsitrim", &self.hsitrim())
288            .field("hsical", &self.hsical())
289            .field("hseon", &self.hseon())
290            .field("hserdy", &self.hserdy())
291            .field("hsebyp", &self.hsebyp())
292            .field("csson", &self.csson())
293            .field("pllon", &self.pllon())
294            .field("pllrdy", &self.pllrdy())
295            .finish()
296    }
297}
298impl W {
299    ///Bit 0 - Internal High Speed clock enable
300    #[inline(always)]
301    pub fn hsion(&mut self) -> HSION_W<CRrs> {
302        HSION_W::new(self, 0)
303    }
304    ///Bits 3:7 - Internal High Speed clock trimming
305    #[inline(always)]
306    pub fn hsitrim(&mut self) -> HSITRIM_W<CRrs> {
307        HSITRIM_W::new(self, 3)
308    }
309    ///Bit 16 - External High Speed clock enable
310    #[inline(always)]
311    pub fn hseon(&mut self) -> HSEON_W<CRrs> {
312        HSEON_W::new(self, 16)
313    }
314    ///Bit 18 - External High Speed clock Bypass
315    #[inline(always)]
316    pub fn hsebyp(&mut self) -> HSEBYP_W<CRrs> {
317        HSEBYP_W::new(self, 18)
318    }
319    ///Bit 19 - Clock Security System enable
320    #[inline(always)]
321    pub fn csson(&mut self) -> CSSON_W<CRrs> {
322        CSSON_W::new(self, 19)
323    }
324    ///Bit 24 - PLL enable
325    #[inline(always)]
326    pub fn pllon(&mut self) -> PLLON_W<CRrs> {
327        PLLON_W::new(self, 24)
328    }
329}
330/**Clock control register
331
332You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
333
334See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:CR)*/
335pub struct CRrs;
336impl crate::RegisterSpec for CRrs {
337    type Ux = u32;
338}
339///`read()` method returns [`cr::R`](R) reader structure
340impl crate::Readable for CRrs {}
341///`write(|w| ..)` method takes [`cr::W`](W) writer structure
342impl crate::Writable for CRrs {
343    type Safety = crate::Unsafe;
344}
345///`reset()` method sets CR to value 0x83
346impl crate::Resettable for CRrs {
347    const RESET_VALUE: u32 = 0x83;
348}
stm32f1/stm32f103/rcc/cr.rs

stm32f1/stm32f103/rcc/
cr.rs
