stm32f1/stm32f103/gpioa/
crh.rs

1///Register `CRH` reader
2pub type R = crate::R<CRHrs>;
3///Register `CRH` writer
4pub type W = crate::W<CRHrs>;
5///Field `CNF(8-15)` reader - Port n.%s configuration bits
6pub use super::crl::CNF_R;
7///Field `CNF(8-15)` writer - Port n.%s configuration bits
8pub use super::crl::CNF_W;
9///Port n.%s configuration bits
10pub use super::crl::CONFIG;
11///Port n.%s mode bits
12pub use super::crl::MODE;
13///Field `MODE(8-15)` reader - Port n.%s mode bits
14pub use super::crl::MODE_R;
15///Field `MODE(8-15)` writer - Port n.%s mode bits
16pub use super::crl::MODE_W;
17impl R {
18    ///Port n.(8-15) mode bits
19    ///
20    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE8` field.</div>
21    #[inline(always)]
22    pub fn mode(&self, n: u8) -> MODE_R {
23        #[allow(clippy::no_effect)]
24        [(); 8][n as usize];
25        MODE_R::new(((self.bits >> (n * 4)) & 3) as u8)
26    }
27    ///Iterator for array of:
28    ///Port n.(8-15) mode bits
29    #[inline(always)]
30    pub fn mode_iter(&self) -> impl Iterator<Item = MODE_R> + '_ {
31        (0..8).map(move |n| MODE_R::new(((self.bits >> (n * 4)) & 3) as u8))
32    }
33    ///Bits 0:1 - Port n.8 mode bits
34    #[inline(always)]
35    pub fn mode8(&self) -> MODE_R {
36        MODE_R::new((self.bits & 3) as u8)
37    }
38    ///Bits 4:5 - Port n.9 mode bits
39    #[inline(always)]
40    pub fn mode9(&self) -> MODE_R {
41        MODE_R::new(((self.bits >> 4) & 3) as u8)
42    }
43    ///Bits 8:9 - Port n.10 mode bits
44    #[inline(always)]
45    pub fn mode10(&self) -> MODE_R {
46        MODE_R::new(((self.bits >> 8) & 3) as u8)
47    }
48    ///Bits 12:13 - Port n.11 mode bits
49    #[inline(always)]
50    pub fn mode11(&self) -> MODE_R {
51        MODE_R::new(((self.bits >> 12) & 3) as u8)
52    }
53    ///Bits 16:17 - Port n.12 mode bits
54    #[inline(always)]
55    pub fn mode12(&self) -> MODE_R {
56        MODE_R::new(((self.bits >> 16) & 3) as u8)
57    }
58    ///Bits 20:21 - Port n.13 mode bits
59    #[inline(always)]
60    pub fn mode13(&self) -> MODE_R {
61        MODE_R::new(((self.bits >> 20) & 3) as u8)
62    }
63    ///Bits 24:25 - Port n.14 mode bits
64    #[inline(always)]
65    pub fn mode14(&self) -> MODE_R {
66        MODE_R::new(((self.bits >> 24) & 3) as u8)
67    }
68    ///Bits 28:29 - Port n.15 mode bits
69    #[inline(always)]
70    pub fn mode15(&self) -> MODE_R {
71        MODE_R::new(((self.bits >> 28) & 3) as u8)
72    }
73    ///Port n.(8-15) configuration bits
74    ///
75    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CNF8` field.</div>
76    #[inline(always)]
77    pub fn cnf(&self, n: u8) -> CNF_R {
78        #[allow(clippy::no_effect)]
79        [(); 8][n as usize];
80        CNF_R::new(((self.bits >> (n * 4 + 2)) & 3) as u8)
81    }
82    ///Iterator for array of:
83    ///Port n.(8-15) configuration bits
84    #[inline(always)]
85    pub fn cnf_iter(&self) -> impl Iterator<Item = CNF_R> + '_ {
86        (0..8).map(move |n| CNF_R::new(((self.bits >> (n * 4 + 2)) & 3) as u8))
87    }
88    ///Bits 2:3 - Port n.8 configuration bits
89    #[inline(always)]
90    pub fn cnf8(&self) -> CNF_R {
91        CNF_R::new(((self.bits >> 2) & 3) as u8)
92    }
93    ///Bits 6:7 - Port n.9 configuration bits
94    #[inline(always)]
95    pub fn cnf9(&self) -> CNF_R {
96        CNF_R::new(((self.bits >> 6) & 3) as u8)
97    }
98    ///Bits 10:11 - Port n.10 configuration bits
99    #[inline(always)]
100    pub fn cnf10(&self) -> CNF_R {
101        CNF_R::new(((self.bits >> 10) & 3) as u8)
102    }
103    ///Bits 14:15 - Port n.11 configuration bits
104    #[inline(always)]
105    pub fn cnf11(&self) -> CNF_R {
106        CNF_R::new(((self.bits >> 14) & 3) as u8)
107    }
108    ///Bits 18:19 - Port n.12 configuration bits
109    #[inline(always)]
110    pub fn cnf12(&self) -> CNF_R {
111        CNF_R::new(((self.bits >> 18) & 3) as u8)
112    }
113    ///Bits 22:23 - Port n.13 configuration bits
114    #[inline(always)]
115    pub fn cnf13(&self) -> CNF_R {
116        CNF_R::new(((self.bits >> 22) & 3) as u8)
117    }
118    ///Bits 26:27 - Port n.14 configuration bits
119    #[inline(always)]
120    pub fn cnf14(&self) -> CNF_R {
121        CNF_R::new(((self.bits >> 26) & 3) as u8)
122    }
123    ///Bits 30:31 - Port n.15 configuration bits
124    #[inline(always)]
125    pub fn cnf15(&self) -> CNF_R {
126        CNF_R::new(((self.bits >> 30) & 3) as u8)
127    }
128}
129impl core::fmt::Debug for R {
130    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
131        f.debug_struct("CRH")
132            .field("mode8", &self.mode8())
133            .field("mode9", &self.mode9())
134            .field("mode10", &self.mode10())
135            .field("mode11", &self.mode11())
136            .field("mode12", &self.mode12())
137            .field("mode13", &self.mode13())
138            .field("mode14", &self.mode14())
139            .field("mode15", &self.mode15())
140            .field("cnf8", &self.cnf8())
141            .field("cnf9", &self.cnf9())
142            .field("cnf10", &self.cnf10())
143            .field("cnf11", &self.cnf11())
144            .field("cnf12", &self.cnf12())
145            .field("cnf13", &self.cnf13())
146            .field("cnf14", &self.cnf14())
147            .field("cnf15", &self.cnf15())
148            .finish()
149    }
150}
151impl W {
152    ///Port n.(8-15) mode bits
153    ///
154    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE8` field.</div>
155    #[inline(always)]
156    pub fn mode(&mut self, n: u8) -> MODE_W<CRHrs> {
157        #[allow(clippy::no_effect)]
158        [(); 8][n as usize];
159        MODE_W::new(self, n * 4)
160    }
161    ///Bits 0:1 - Port n.8 mode bits
162    #[inline(always)]
163    pub fn mode8(&mut self) -> MODE_W<CRHrs> {
164        MODE_W::new(self, 0)
165    }
166    ///Bits 4:5 - Port n.9 mode bits
167    #[inline(always)]
168    pub fn mode9(&mut self) -> MODE_W<CRHrs> {
169        MODE_W::new(self, 4)
170    }
171    ///Bits 8:9 - Port n.10 mode bits
172    #[inline(always)]
173    pub fn mode10(&mut self) -> MODE_W<CRHrs> {
174        MODE_W::new(self, 8)
175    }
176    ///Bits 12:13 - Port n.11 mode bits
177    #[inline(always)]
178    pub fn mode11(&mut self) -> MODE_W<CRHrs> {
179        MODE_W::new(self, 12)
180    }
181    ///Bits 16:17 - Port n.12 mode bits
182    #[inline(always)]
183    pub fn mode12(&mut self) -> MODE_W<CRHrs> {
184        MODE_W::new(self, 16)
185    }
186    ///Bits 20:21 - Port n.13 mode bits
187    #[inline(always)]
188    pub fn mode13(&mut self) -> MODE_W<CRHrs> {
189        MODE_W::new(self, 20)
190    }
191    ///Bits 24:25 - Port n.14 mode bits
192    #[inline(always)]
193    pub fn mode14(&mut self) -> MODE_W<CRHrs> {
194        MODE_W::new(self, 24)
195    }
196    ///Bits 28:29 - Port n.15 mode bits
197    #[inline(always)]
198    pub fn mode15(&mut self) -> MODE_W<CRHrs> {
199        MODE_W::new(self, 28)
200    }
201    ///Port n.(8-15) configuration bits
202    ///
203    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CNF8` field.</div>
204    #[inline(always)]
205    pub fn cnf(&mut self, n: u8) -> CNF_W<CRHrs> {
206        #[allow(clippy::no_effect)]
207        [(); 8][n as usize];
208        CNF_W::new(self, n * 4 + 2)
209    }
210    ///Bits 2:3 - Port n.8 configuration bits
211    #[inline(always)]
212    pub fn cnf8(&mut self) -> CNF_W<CRHrs> {
213        CNF_W::new(self, 2)
214    }
215    ///Bits 6:7 - Port n.9 configuration bits
216    #[inline(always)]
217    pub fn cnf9(&mut self) -> CNF_W<CRHrs> {
218        CNF_W::new(self, 6)
219    }
220    ///Bits 10:11 - Port n.10 configuration bits
221    #[inline(always)]
222    pub fn cnf10(&mut self) -> CNF_W<CRHrs> {
223        CNF_W::new(self, 10)
224    }
225    ///Bits 14:15 - Port n.11 configuration bits
226    #[inline(always)]
227    pub fn cnf11(&mut self) -> CNF_W<CRHrs> {
228        CNF_W::new(self, 14)
229    }
230    ///Bits 18:19 - Port n.12 configuration bits
231    #[inline(always)]
232    pub fn cnf12(&mut self) -> CNF_W<CRHrs> {
233        CNF_W::new(self, 18)
234    }
235    ///Bits 22:23 - Port n.13 configuration bits
236    #[inline(always)]
237    pub fn cnf13(&mut self) -> CNF_W<CRHrs> {
238        CNF_W::new(self, 22)
239    }
240    ///Bits 26:27 - Port n.14 configuration bits
241    #[inline(always)]
242    pub fn cnf14(&mut self) -> CNF_W<CRHrs> {
243        CNF_W::new(self, 26)
244    }
245    ///Bits 30:31 - Port n.15 configuration bits
246    #[inline(always)]
247    pub fn cnf15(&mut self) -> CNF_W<CRHrs> {
248        CNF_W::new(self, 30)
249    }
250}
251/**Port configuration register high (GPIOn_CRL)
252
253You can [`read`](crate::Reg::read) this register and get [`crh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
254
255See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA:CRH)*/
256pub struct CRHrs;
257impl crate::RegisterSpec for CRHrs {
258    type Ux = u32;
259}
260///`read()` method returns [`crh::R`](R) reader structure
261impl crate::Readable for CRHrs {}
262///`write(|w| ..)` method takes [`crh::W`](W) writer structure
263impl crate::Writable for CRHrs {
264    type Safety = crate::Unsafe;
265}
266///`reset()` method sets CRH to value 0x4444_4444
267impl crate::Resettable for CRHrs {
268    const RESET_VALUE: u32 = 0x4444_4444;
269}
stm32f1/stm32f103/gpioa/crh.rs

stm32f1/stm32f103/gpioa/
crh.rs
