stm32f1/stm32f103/exti/
rtsr.rs

1///Register `RTSR` reader
2pub type R = crate::R<RTSRrs>;
3///Register `RTSR` writer
4pub type W = crate::W<RTSRrs>;
5/**Rising trigger event configuration of line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RISING_TRIGGER {
11    ///0: Rising edge trigger is disabled
12    Disabled = 0,
13    ///1: Rising edge trigger is enabled
14    Enabled = 1,
15}
16impl From<RISING_TRIGGER> for bool {
17    #[inline(always)]
18    fn from(variant: RISING_TRIGGER) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `TR(0-18)` reader - Rising trigger event configuration of line %s
23pub type TR_R = crate::BitReader<RISING_TRIGGER>;
24impl TR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RISING_TRIGGER {
28        match self.bits {
29            false => RISING_TRIGGER::Disabled,
30            true => RISING_TRIGGER::Enabled,
31        }
32    }
33    ///Rising edge trigger is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == RISING_TRIGGER::Disabled
37    }
38    ///Rising edge trigger is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == RISING_TRIGGER::Enabled
42    }
43}
44///Field `TR(0-18)` writer - Rising trigger event configuration of line %s
45pub type TR_W<'a, REG> = crate::BitWriter<'a, REG, RISING_TRIGGER>;
46impl<'a, REG> TR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Rising edge trigger is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(RISING_TRIGGER::Disabled)
54    }
55    ///Rising edge trigger is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(RISING_TRIGGER::Enabled)
59    }
60}
61impl R {
62    ///Rising trigger event configuration of line (0-18)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TR0` field.</div>
65    #[inline(always)]
66    pub fn tr(&self, n: u8) -> TR_R {
67        #[allow(clippy::no_effect)]
68        [(); 19][n as usize];
69        TR_R::new(((self.bits >> n) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///Rising trigger event configuration of line (0-18)
73    #[inline(always)]
74    pub fn tr_iter(&self) -> impl Iterator<Item = TR_R> + '_ {
75        (0..19).map(move |n| TR_R::new(((self.bits >> n) & 1) != 0))
76    }
77    ///Bit 0 - Rising trigger event configuration of line 0
78    #[inline(always)]
79    pub fn tr0(&self) -> TR_R {
80        TR_R::new((self.bits & 1) != 0)
81    }
82    ///Bit 1 - Rising trigger event configuration of line 1
83    #[inline(always)]
84    pub fn tr1(&self) -> TR_R {
85        TR_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    ///Bit 2 - Rising trigger event configuration of line 2
88    #[inline(always)]
89    pub fn tr2(&self) -> TR_R {
90        TR_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    ///Bit 3 - Rising trigger event configuration of line 3
93    #[inline(always)]
94    pub fn tr3(&self) -> TR_R {
95        TR_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    ///Bit 4 - Rising trigger event configuration of line 4
98    #[inline(always)]
99    pub fn tr4(&self) -> TR_R {
100        TR_R::new(((self.bits >> 4) & 1) != 0)
101    }
102    ///Bit 5 - Rising trigger event configuration of line 5
103    #[inline(always)]
104    pub fn tr5(&self) -> TR_R {
105        TR_R::new(((self.bits >> 5) & 1) != 0)
106    }
107    ///Bit 6 - Rising trigger event configuration of line 6
108    #[inline(always)]
109    pub fn tr6(&self) -> TR_R {
110        TR_R::new(((self.bits >> 6) & 1) != 0)
111    }
112    ///Bit 7 - Rising trigger event configuration of line 7
113    #[inline(always)]
114    pub fn tr7(&self) -> TR_R {
115        TR_R::new(((self.bits >> 7) & 1) != 0)
116    }
117    ///Bit 8 - Rising trigger event configuration of line 8
118    #[inline(always)]
119    pub fn tr8(&self) -> TR_R {
120        TR_R::new(((self.bits >> 8) & 1) != 0)
121    }
122    ///Bit 9 - Rising trigger event configuration of line 9
123    #[inline(always)]
124    pub fn tr9(&self) -> TR_R {
125        TR_R::new(((self.bits >> 9) & 1) != 0)
126    }
127    ///Bit 10 - Rising trigger event configuration of line 10
128    #[inline(always)]
129    pub fn tr10(&self) -> TR_R {
130        TR_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 11 - Rising trigger event configuration of line 11
133    #[inline(always)]
134    pub fn tr11(&self) -> TR_R {
135        TR_R::new(((self.bits >> 11) & 1) != 0)
136    }
137    ///Bit 12 - Rising trigger event configuration of line 12
138    #[inline(always)]
139    pub fn tr12(&self) -> TR_R {
140        TR_R::new(((self.bits >> 12) & 1) != 0)
141    }
142    ///Bit 13 - Rising trigger event configuration of line 13
143    #[inline(always)]
144    pub fn tr13(&self) -> TR_R {
145        TR_R::new(((self.bits >> 13) & 1) != 0)
146    }
147    ///Bit 14 - Rising trigger event configuration of line 14
148    #[inline(always)]
149    pub fn tr14(&self) -> TR_R {
150        TR_R::new(((self.bits >> 14) & 1) != 0)
151    }
152    ///Bit 15 - Rising trigger event configuration of line 15
153    #[inline(always)]
154    pub fn tr15(&self) -> TR_R {
155        TR_R::new(((self.bits >> 15) & 1) != 0)
156    }
157    ///Bit 16 - Rising trigger event configuration of line 16
158    #[inline(always)]
159    pub fn tr16(&self) -> TR_R {
160        TR_R::new(((self.bits >> 16) & 1) != 0)
161    }
162    ///Bit 17 - Rising trigger event configuration of line 17
163    #[inline(always)]
164    pub fn tr17(&self) -> TR_R {
165        TR_R::new(((self.bits >> 17) & 1) != 0)
166    }
167    ///Bit 18 - Rising trigger event configuration of line 18
168    #[inline(always)]
169    pub fn tr18(&self) -> TR_R {
170        TR_R::new(((self.bits >> 18) & 1) != 0)
171    }
172}
173impl core::fmt::Debug for R {
174    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
175        f.debug_struct("RTSR")
176            .field("tr0", &self.tr0())
177            .field("tr1", &self.tr1())
178            .field("tr2", &self.tr2())
179            .field("tr3", &self.tr3())
180            .field("tr4", &self.tr4())
181            .field("tr5", &self.tr5())
182            .field("tr6", &self.tr6())
183            .field("tr7", &self.tr7())
184            .field("tr8", &self.tr8())
185            .field("tr9", &self.tr9())
186            .field("tr10", &self.tr10())
187            .field("tr11", &self.tr11())
188            .field("tr12", &self.tr12())
189            .field("tr13", &self.tr13())
190            .field("tr14", &self.tr14())
191            .field("tr15", &self.tr15())
192            .field("tr16", &self.tr16())
193            .field("tr17", &self.tr17())
194            .field("tr18", &self.tr18())
195            .finish()
196    }
197}
198impl W {
199    ///Rising trigger event configuration of line (0-18)
200    ///
201    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TR0` field.</div>
202    #[inline(always)]
203    pub fn tr(&mut self, n: u8) -> TR_W<RTSRrs> {
204        #[allow(clippy::no_effect)]
205        [(); 19][n as usize];
206        TR_W::new(self, n)
207    }
208    ///Bit 0 - Rising trigger event configuration of line 0
209    #[inline(always)]
210    pub fn tr0(&mut self) -> TR_W<RTSRrs> {
211        TR_W::new(self, 0)
212    }
213    ///Bit 1 - Rising trigger event configuration of line 1
214    #[inline(always)]
215    pub fn tr1(&mut self) -> TR_W<RTSRrs> {
216        TR_W::new(self, 1)
217    }
218    ///Bit 2 - Rising trigger event configuration of line 2
219    #[inline(always)]
220    pub fn tr2(&mut self) -> TR_W<RTSRrs> {
221        TR_W::new(self, 2)
222    }
223    ///Bit 3 - Rising trigger event configuration of line 3
224    #[inline(always)]
225    pub fn tr3(&mut self) -> TR_W<RTSRrs> {
226        TR_W::new(self, 3)
227    }
228    ///Bit 4 - Rising trigger event configuration of line 4
229    #[inline(always)]
230    pub fn tr4(&mut self) -> TR_W<RTSRrs> {
231        TR_W::new(self, 4)
232    }
233    ///Bit 5 - Rising trigger event configuration of line 5
234    #[inline(always)]
235    pub fn tr5(&mut self) -> TR_W<RTSRrs> {
236        TR_W::new(self, 5)
237    }
238    ///Bit 6 - Rising trigger event configuration of line 6
239    #[inline(always)]
240    pub fn tr6(&mut self) -> TR_W<RTSRrs> {
241        TR_W::new(self, 6)
242    }
243    ///Bit 7 - Rising trigger event configuration of line 7
244    #[inline(always)]
245    pub fn tr7(&mut self) -> TR_W<RTSRrs> {
246        TR_W::new(self, 7)
247    }
248    ///Bit 8 - Rising trigger event configuration of line 8
249    #[inline(always)]
250    pub fn tr8(&mut self) -> TR_W<RTSRrs> {
251        TR_W::new(self, 8)
252    }
253    ///Bit 9 - Rising trigger event configuration of line 9
254    #[inline(always)]
255    pub fn tr9(&mut self) -> TR_W<RTSRrs> {
256        TR_W::new(self, 9)
257    }
258    ///Bit 10 - Rising trigger event configuration of line 10
259    #[inline(always)]
260    pub fn tr10(&mut self) -> TR_W<RTSRrs> {
261        TR_W::new(self, 10)
262    }
263    ///Bit 11 - Rising trigger event configuration of line 11
264    #[inline(always)]
265    pub fn tr11(&mut self) -> TR_W<RTSRrs> {
266        TR_W::new(self, 11)
267    }
268    ///Bit 12 - Rising trigger event configuration of line 12
269    #[inline(always)]
270    pub fn tr12(&mut self) -> TR_W<RTSRrs> {
271        TR_W::new(self, 12)
272    }
273    ///Bit 13 - Rising trigger event configuration of line 13
274    #[inline(always)]
275    pub fn tr13(&mut self) -> TR_W<RTSRrs> {
276        TR_W::new(self, 13)
277    }
278    ///Bit 14 - Rising trigger event configuration of line 14
279    #[inline(always)]
280    pub fn tr14(&mut self) -> TR_W<RTSRrs> {
281        TR_W::new(self, 14)
282    }
283    ///Bit 15 - Rising trigger event configuration of line 15
284    #[inline(always)]
285    pub fn tr15(&mut self) -> TR_W<RTSRrs> {
286        TR_W::new(self, 15)
287    }
288    ///Bit 16 - Rising trigger event configuration of line 16
289    #[inline(always)]
290    pub fn tr16(&mut self) -> TR_W<RTSRrs> {
291        TR_W::new(self, 16)
292    }
293    ///Bit 17 - Rising trigger event configuration of line 17
294    #[inline(always)]
295    pub fn tr17(&mut self) -> TR_W<RTSRrs> {
296        TR_W::new(self, 17)
297    }
298    ///Bit 18 - Rising trigger event configuration of line 18
299    #[inline(always)]
300    pub fn tr18(&mut self) -> TR_W<RTSRrs> {
301        TR_W::new(self, 18)
302    }
303}
304/**Rising Trigger selection register (EXTI_RTSR)
305
306You can [`read`](crate::Reg::read) this register and get [`rtsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
307
308See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#EXTI:RTSR)*/
309pub struct RTSRrs;
310impl crate::RegisterSpec for RTSRrs {
311    type Ux = u32;
312}
313///`read()` method returns [`rtsr::R`](R) reader structure
314impl crate::Readable for RTSRrs {}
315///`write(|w| ..)` method takes [`rtsr::W`](W) writer structure
316impl crate::Writable for RTSRrs {
317    type Safety = crate::Unsafe;
318}
319///`reset()` method sets RTSR to value 0
320impl crate::Resettable for RTSRrs {}
stm32f1/stm32f103/exti/rtsr.rs

stm32f1/stm32f103/exti/
rtsr.rs
