stm32f1/stm32f103/dac/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**DAC channel%s enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EN1 {
11    ///0: DAC channel X disabled
12    Disabled = 0,
13    ///1: DAC channel X enabled
14    Enabled = 1,
15}
16impl From<EN1> for bool {
17    #[inline(always)]
18    fn from(variant: EN1) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EN(1-2)` reader - DAC channel%s enable
23pub type EN_R = crate::BitReader<EN1>;
24impl EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EN1 {
28        match self.bits {
29            false => EN1::Disabled,
30            true => EN1::Enabled,
31        }
32    }
33    ///DAC channel X disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EN1::Disabled
37    }
38    ///DAC channel X enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EN1::Enabled
42    }
43}
44///Field `EN(1-2)` writer - DAC channel%s enable
45pub type EN_W<'a, REG> = crate::BitWriter<'a, REG, EN1>;
46impl<'a, REG> EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///DAC channel X disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EN1::Disabled)
54    }
55    ///DAC channel X enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EN1::Enabled)
59    }
60}
61/**DAC channel%s output buffer disable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum BOFF1 {
67    ///0: DAC channel X output buffer enabled
68    Enabled = 0,
69    ///1: DAC channel X output buffer disabled
70    Disabled = 1,
71}
72impl From<BOFF1> for bool {
73    #[inline(always)]
74    fn from(variant: BOFF1) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `BOFF(1-2)` reader - DAC channel%s output buffer disable
79pub type BOFF_R = crate::BitReader<BOFF1>;
80impl BOFF_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> BOFF1 {
84        match self.bits {
85            false => BOFF1::Enabled,
86            true => BOFF1::Disabled,
87        }
88    }
89    ///DAC channel X output buffer enabled
90    #[inline(always)]
91    pub fn is_enabled(&self) -> bool {
92        *self == BOFF1::Enabled
93    }
94    ///DAC channel X output buffer disabled
95    #[inline(always)]
96    pub fn is_disabled(&self) -> bool {
97        *self == BOFF1::Disabled
98    }
99}
100///Field `BOFF(1-2)` writer - DAC channel%s output buffer disable
101pub type BOFF_W<'a, REG> = crate::BitWriter<'a, REG, BOFF1>;
102impl<'a, REG> BOFF_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///DAC channel X output buffer enabled
107    #[inline(always)]
108    pub fn enabled(self) -> &'a mut crate::W<REG> {
109        self.variant(BOFF1::Enabled)
110    }
111    ///DAC channel X output buffer disabled
112    #[inline(always)]
113    pub fn disabled(self) -> &'a mut crate::W<REG> {
114        self.variant(BOFF1::Disabled)
115    }
116}
117/**DAC channel%s trigger enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum TEN1 {
123    ///0: DAC channel X trigger disabled
124    Disabled = 0,
125    ///1: DAC channel X trigger enabled
126    Enabled = 1,
127}
128impl From<TEN1> for bool {
129    #[inline(always)]
130    fn from(variant: TEN1) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `TEN(1-2)` reader - DAC channel%s trigger enable
135pub type TEN_R = crate::BitReader<TEN1>;
136impl TEN_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> TEN1 {
140        match self.bits {
141            false => TEN1::Disabled,
142            true => TEN1::Enabled,
143        }
144    }
145    ///DAC channel X trigger disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == TEN1::Disabled
149    }
150    ///DAC channel X trigger enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == TEN1::Enabled
154    }
155}
156///Field `TEN(1-2)` writer - DAC channel%s trigger enable
157pub type TEN_W<'a, REG> = crate::BitWriter<'a, REG, TEN1>;
158impl<'a, REG> TEN_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///DAC channel X trigger disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(TEN1::Disabled)
166    }
167    ///DAC channel X trigger enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(TEN1::Enabled)
171    }
172}
173/**DAC channel1 trigger selection
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178#[repr(u8)]
179pub enum TSEL1 {
180    ///0: Timer 6 TRGO event
181    Tim6trgo = 0,
182    ///1: Timer 8 TRGO event
183    Tim8trgo = 1,
184    ///2: Timer 7 TRGO event
185    Tim7trgo = 2,
186    ///3: Timer 5 TRGO event
187    Tim5trgo = 3,
188    ///4: Timer 2 TRGO event
189    Tim2trgo = 4,
190    ///5: Timer 4 TRGO event
191    Tim4trgo = 5,
192    ///6: EXTI line 9
193    Exti9 = 6,
194    ///7: Software trigger
195    Swtrig = 7,
196}
197impl From<TSEL1> for u8 {
198    #[inline(always)]
199    fn from(variant: TSEL1) -> Self {
200        variant as _
201    }
202}
203impl crate::FieldSpec for TSEL1 {
204    type Ux = u8;
205}
206impl crate::IsEnum for TSEL1 {}
207///Field `TSEL1` reader - DAC channel1 trigger selection
208pub type TSEL1_R = crate::FieldReader<TSEL1>;
209impl TSEL1_R {
210    ///Get enumerated values variant
211    #[inline(always)]
212    pub const fn variant(&self) -> TSEL1 {
213        match self.bits {
214            0 => TSEL1::Tim6trgo,
215            1 => TSEL1::Tim8trgo,
216            2 => TSEL1::Tim7trgo,
217            3 => TSEL1::Tim5trgo,
218            4 => TSEL1::Tim2trgo,
219            5 => TSEL1::Tim4trgo,
220            6 => TSEL1::Exti9,
221            7 => TSEL1::Swtrig,
222            _ => unreachable!(),
223        }
224    }
225    ///Timer 6 TRGO event
226    #[inline(always)]
227    pub fn is_tim6trgo(&self) -> bool {
228        *self == TSEL1::Tim6trgo
229    }
230    ///Timer 8 TRGO event
231    #[inline(always)]
232    pub fn is_tim8trgo(&self) -> bool {
233        *self == TSEL1::Tim8trgo
234    }
235    ///Timer 7 TRGO event
236    #[inline(always)]
237    pub fn is_tim7trgo(&self) -> bool {
238        *self == TSEL1::Tim7trgo
239    }
240    ///Timer 5 TRGO event
241    #[inline(always)]
242    pub fn is_tim5trgo(&self) -> bool {
243        *self == TSEL1::Tim5trgo
244    }
245    ///Timer 2 TRGO event
246    #[inline(always)]
247    pub fn is_tim2trgo(&self) -> bool {
248        *self == TSEL1::Tim2trgo
249    }
250    ///Timer 4 TRGO event
251    #[inline(always)]
252    pub fn is_tim4trgo(&self) -> bool {
253        *self == TSEL1::Tim4trgo
254    }
255    ///EXTI line 9
256    #[inline(always)]
257    pub fn is_exti9(&self) -> bool {
258        *self == TSEL1::Exti9
259    }
260    ///Software trigger
261    #[inline(always)]
262    pub fn is_swtrig(&self) -> bool {
263        *self == TSEL1::Swtrig
264    }
265}
266///Field `TSEL1` writer - DAC channel1 trigger selection
267pub type TSEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TSEL1, crate::Safe>;
268impl<'a, REG> TSEL1_W<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271    REG::Ux: From<u8>,
272{
273    ///Timer 6 TRGO event
274    #[inline(always)]
275    pub fn tim6trgo(self) -> &'a mut crate::W<REG> {
276        self.variant(TSEL1::Tim6trgo)
277    }
278    ///Timer 8 TRGO event
279    #[inline(always)]
280    pub fn tim8trgo(self) -> &'a mut crate::W<REG> {
281        self.variant(TSEL1::Tim8trgo)
282    }
283    ///Timer 7 TRGO event
284    #[inline(always)]
285    pub fn tim7trgo(self) -> &'a mut crate::W<REG> {
286        self.variant(TSEL1::Tim7trgo)
287    }
288    ///Timer 5 TRGO event
289    #[inline(always)]
290    pub fn tim5trgo(self) -> &'a mut crate::W<REG> {
291        self.variant(TSEL1::Tim5trgo)
292    }
293    ///Timer 2 TRGO event
294    #[inline(always)]
295    pub fn tim2trgo(self) -> &'a mut crate::W<REG> {
296        self.variant(TSEL1::Tim2trgo)
297    }
298    ///Timer 4 TRGO event
299    #[inline(always)]
300    pub fn tim4trgo(self) -> &'a mut crate::W<REG> {
301        self.variant(TSEL1::Tim4trgo)
302    }
303    ///EXTI line 9
304    #[inline(always)]
305    pub fn exti9(self) -> &'a mut crate::W<REG> {
306        self.variant(TSEL1::Exti9)
307    }
308    ///Software trigger
309    #[inline(always)]
310    pub fn swtrig(self) -> &'a mut crate::W<REG> {
311        self.variant(TSEL1::Swtrig)
312    }
313}
314/**DAC channel%s noise/triangle wave generation enable
315
316Value on reset: 0*/
317#[cfg_attr(feature = "defmt", derive(defmt::Format))]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319#[repr(u8)]
320pub enum WAVE1 {
321    ///0: Wave generation disabled
322    Disabled = 0,
323    ///1: Noise wave generation enabled
324    Noise = 1,
325    ///2: Triangle wave generation enabled
326    Triangle = 2,
327}
328impl From<WAVE1> for u8 {
329    #[inline(always)]
330    fn from(variant: WAVE1) -> Self {
331        variant as _
332    }
333}
334impl crate::FieldSpec for WAVE1 {
335    type Ux = u8;
336}
337impl crate::IsEnum for WAVE1 {}
338///Field `WAVE(1-2)` reader - DAC channel%s noise/triangle wave generation enable
339pub type WAVE_R = crate::FieldReader<WAVE1>;
340impl WAVE_R {
341    ///Get enumerated values variant
342    #[inline(always)]
343    pub const fn variant(&self) -> WAVE1 {
344        match self.bits {
345            0 => WAVE1::Disabled,
346            1 => WAVE1::Noise,
347            _ => WAVE1::Triangle,
348        }
349    }
350    ///Wave generation disabled
351    #[inline(always)]
352    pub fn is_disabled(&self) -> bool {
353        *self == WAVE1::Disabled
354    }
355    ///Noise wave generation enabled
356    #[inline(always)]
357    pub fn is_noise(&self) -> bool {
358        *self == WAVE1::Noise
359    }
360    ///Triangle wave generation enabled
361    #[inline(always)]
362    pub fn is_triangle(&self) -> bool {
363        matches!(self.variant(), WAVE1::Triangle)
364    }
365}
366///Field `WAVE(1-2)` writer - DAC channel%s noise/triangle wave generation enable
367pub type WAVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WAVE1, crate::Safe>;
368impl<'a, REG> WAVE_W<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371    REG::Ux: From<u8>,
372{
373    ///Wave generation disabled
374    #[inline(always)]
375    pub fn disabled(self) -> &'a mut crate::W<REG> {
376        self.variant(WAVE1::Disabled)
377    }
378    ///Noise wave generation enabled
379    #[inline(always)]
380    pub fn noise(self) -> &'a mut crate::W<REG> {
381        self.variant(WAVE1::Noise)
382    }
383    ///Triangle wave generation enabled
384    #[inline(always)]
385    pub fn triangle(self) -> &'a mut crate::W<REG> {
386        self.variant(WAVE1::Triangle)
387    }
388}
389/**DAC channel%s mask/amplitude selector
390
391Value on reset: 0*/
392#[cfg_attr(feature = "defmt", derive(defmt::Format))]
393#[derive(Clone, Copy, Debug, PartialEq, Eq)]
394#[repr(u8)]
395pub enum MAMP1 {
396    ///0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
397    Amp1 = 0,
398    ///1: Unmask bits\[1:0\] of LFSR/ triangle amplitude equal to 3
399    Amp3 = 1,
400    ///2: Unmask bits\[2:0\] of LFSR/ triangle amplitude equal to 7
401    Amp7 = 2,
402    ///3: Unmask bits\[3:0\] of LFSR/ triangle amplitude equal to 15
403    Amp15 = 3,
404    ///4: Unmask bits\[4:0\] of LFSR/ triangle amplitude equal to 31
405    Amp31 = 4,
406    ///5: Unmask bits\[5:0\] of LFSR/ triangle amplitude equal 63
407    Amp63 = 5,
408    ///6: Unmask bits\[6:0\] of LFSR/ triangle amplitude equal to 127
409    Amp127 = 6,
410    ///7: Unmask bits\[7:0\] of LFSR/ triangle amplitude equal to 255
411    Amp255 = 7,
412    ///8: Unmask bits\[8:0\] of LFSR/ triangle amplitude equal to 511
413    Amp511 = 8,
414    ///9: Unmask bits\[9:0\] of LFSR/ triangle amplitude equal to 1023
415    Amp1023 = 9,
416    ///10: Unmask bits\[10:0\] of LFSR/ triangle amplitude equal to 2047
417    Amp2047 = 10,
418    ///11: Unmask bits\[11:0\] of LFSR/ triangle amplitude equal to 4095
419    Amp4095 = 11,
420}
421impl From<MAMP1> for u8 {
422    #[inline(always)]
423    fn from(variant: MAMP1) -> Self {
424        variant as _
425    }
426}
427impl crate::FieldSpec for MAMP1 {
428    type Ux = u8;
429}
430impl crate::IsEnum for MAMP1 {}
431///Field `MAMP(1-2)` reader - DAC channel%s mask/amplitude selector
432pub type MAMP_R = crate::FieldReader<MAMP1>;
433impl MAMP_R {
434    ///Get enumerated values variant
435    #[inline(always)]
436    pub const fn variant(&self) -> MAMP1 {
437        match self.bits {
438            0 => MAMP1::Amp1,
439            1 => MAMP1::Amp3,
440            2 => MAMP1::Amp7,
441            3 => MAMP1::Amp15,
442            4 => MAMP1::Amp31,
443            5 => MAMP1::Amp63,
444            6 => MAMP1::Amp127,
445            7 => MAMP1::Amp255,
446            8 => MAMP1::Amp511,
447            9 => MAMP1::Amp1023,
448            10 => MAMP1::Amp2047,
449            _ => MAMP1::Amp4095,
450        }
451    }
452    ///Unmask bit0 of LFSR/ triangle amplitude equal to 1
453    #[inline(always)]
454    pub fn is_amp1(&self) -> bool {
455        *self == MAMP1::Amp1
456    }
457    ///Unmask bits\[1:0\] of LFSR/ triangle amplitude equal to 3
458    #[inline(always)]
459    pub fn is_amp3(&self) -> bool {
460        *self == MAMP1::Amp3
461    }
462    ///Unmask bits\[2:0\] of LFSR/ triangle amplitude equal to 7
463    #[inline(always)]
464    pub fn is_amp7(&self) -> bool {
465        *self == MAMP1::Amp7
466    }
467    ///Unmask bits\[3:0\] of LFSR/ triangle amplitude equal to 15
468    #[inline(always)]
469    pub fn is_amp15(&self) -> bool {
470        *self == MAMP1::Amp15
471    }
472    ///Unmask bits\[4:0\] of LFSR/ triangle amplitude equal to 31
473    #[inline(always)]
474    pub fn is_amp31(&self) -> bool {
475        *self == MAMP1::Amp31
476    }
477    ///Unmask bits\[5:0\] of LFSR/ triangle amplitude equal 63
478    #[inline(always)]
479    pub fn is_amp63(&self) -> bool {
480        *self == MAMP1::Amp63
481    }
482    ///Unmask bits\[6:0\] of LFSR/ triangle amplitude equal to 127
483    #[inline(always)]
484    pub fn is_amp127(&self) -> bool {
485        *self == MAMP1::Amp127
486    }
487    ///Unmask bits\[7:0\] of LFSR/ triangle amplitude equal to 255
488    #[inline(always)]
489    pub fn is_amp255(&self) -> bool {
490        *self == MAMP1::Amp255
491    }
492    ///Unmask bits\[8:0\] of LFSR/ triangle amplitude equal to 511
493    #[inline(always)]
494    pub fn is_amp511(&self) -> bool {
495        *self == MAMP1::Amp511
496    }
497    ///Unmask bits\[9:0\] of LFSR/ triangle amplitude equal to 1023
498    #[inline(always)]
499    pub fn is_amp1023(&self) -> bool {
500        *self == MAMP1::Amp1023
501    }
502    ///Unmask bits\[10:0\] of LFSR/ triangle amplitude equal to 2047
503    #[inline(always)]
504    pub fn is_amp2047(&self) -> bool {
505        *self == MAMP1::Amp2047
506    }
507    ///Unmask bits\[11:0\] of LFSR/ triangle amplitude equal to 4095
508    #[inline(always)]
509    pub fn is_amp4095(&self) -> bool {
510        matches!(self.variant(), MAMP1::Amp4095)
511    }
512}
513///Field `MAMP(1-2)` writer - DAC channel%s mask/amplitude selector
514pub type MAMP_W<'a, REG> = crate::FieldWriter<'a, REG, 4, MAMP1, crate::Safe>;
515impl<'a, REG> MAMP_W<'a, REG>
516where
517    REG: crate::Writable + crate::RegisterSpec,
518    REG::Ux: From<u8>,
519{
520    ///Unmask bit0 of LFSR/ triangle amplitude equal to 1
521    #[inline(always)]
522    pub fn amp1(self) -> &'a mut crate::W<REG> {
523        self.variant(MAMP1::Amp1)
524    }
525    ///Unmask bits\[1:0\] of LFSR/ triangle amplitude equal to 3
526    #[inline(always)]
527    pub fn amp3(self) -> &'a mut crate::W<REG> {
528        self.variant(MAMP1::Amp3)
529    }
530    ///Unmask bits\[2:0\] of LFSR/ triangle amplitude equal to 7
531    #[inline(always)]
532    pub fn amp7(self) -> &'a mut crate::W<REG> {
533        self.variant(MAMP1::Amp7)
534    }
535    ///Unmask bits\[3:0\] of LFSR/ triangle amplitude equal to 15
536    #[inline(always)]
537    pub fn amp15(self) -> &'a mut crate::W<REG> {
538        self.variant(MAMP1::Amp15)
539    }
540    ///Unmask bits\[4:0\] of LFSR/ triangle amplitude equal to 31
541    #[inline(always)]
542    pub fn amp31(self) -> &'a mut crate::W<REG> {
543        self.variant(MAMP1::Amp31)
544    }
545    ///Unmask bits\[5:0\] of LFSR/ triangle amplitude equal 63
546    #[inline(always)]
547    pub fn amp63(self) -> &'a mut crate::W<REG> {
548        self.variant(MAMP1::Amp63)
549    }
550    ///Unmask bits\[6:0\] of LFSR/ triangle amplitude equal to 127
551    #[inline(always)]
552    pub fn amp127(self) -> &'a mut crate::W<REG> {
553        self.variant(MAMP1::Amp127)
554    }
555    ///Unmask bits\[7:0\] of LFSR/ triangle amplitude equal to 255
556    #[inline(always)]
557    pub fn amp255(self) -> &'a mut crate::W<REG> {
558        self.variant(MAMP1::Amp255)
559    }
560    ///Unmask bits\[8:0\] of LFSR/ triangle amplitude equal to 511
561    #[inline(always)]
562    pub fn amp511(self) -> &'a mut crate::W<REG> {
563        self.variant(MAMP1::Amp511)
564    }
565    ///Unmask bits\[9:0\] of LFSR/ triangle amplitude equal to 1023
566    #[inline(always)]
567    pub fn amp1023(self) -> &'a mut crate::W<REG> {
568        self.variant(MAMP1::Amp1023)
569    }
570    ///Unmask bits\[10:0\] of LFSR/ triangle amplitude equal to 2047
571    #[inline(always)]
572    pub fn amp2047(self) -> &'a mut crate::W<REG> {
573        self.variant(MAMP1::Amp2047)
574    }
575    ///Unmask bits\[11:0\] of LFSR/ triangle amplitude equal to 4095
576    #[inline(always)]
577    pub fn amp4095(self) -> &'a mut crate::W<REG> {
578        self.variant(MAMP1::Amp4095)
579    }
580}
581/**DAC channel%s DMA enable
582
583Value on reset: 0*/
584#[cfg_attr(feature = "defmt", derive(defmt::Format))]
585#[derive(Clone, Copy, Debug, PartialEq, Eq)]
586pub enum DMAEN1 {
587    ///0: DAC channel X DMA mode disabled
588    Disabled = 0,
589    ///1: DAC channel X DMA mode enabled
590    Enabled = 1,
591}
592impl From<DMAEN1> for bool {
593    #[inline(always)]
594    fn from(variant: DMAEN1) -> Self {
595        variant as u8 != 0
596    }
597}
598///Field `DMAEN(1-2)` reader - DAC channel%s DMA enable
599pub type DMAEN_R = crate::BitReader<DMAEN1>;
600impl DMAEN_R {
601    ///Get enumerated values variant
602    #[inline(always)]
603    pub const fn variant(&self) -> DMAEN1 {
604        match self.bits {
605            false => DMAEN1::Disabled,
606            true => DMAEN1::Enabled,
607        }
608    }
609    ///DAC channel X DMA mode disabled
610    #[inline(always)]
611    pub fn is_disabled(&self) -> bool {
612        *self == DMAEN1::Disabled
613    }
614    ///DAC channel X DMA mode enabled
615    #[inline(always)]
616    pub fn is_enabled(&self) -> bool {
617        *self == DMAEN1::Enabled
618    }
619}
620///Field `DMAEN(1-2)` writer - DAC channel%s DMA enable
621pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN1>;
622impl<'a, REG> DMAEN_W<'a, REG>
623where
624    REG: crate::Writable + crate::RegisterSpec,
625{
626    ///DAC channel X DMA mode disabled
627    #[inline(always)]
628    pub fn disabled(self) -> &'a mut crate::W<REG> {
629        self.variant(DMAEN1::Disabled)
630    }
631    ///DAC channel X DMA mode enabled
632    #[inline(always)]
633    pub fn enabled(self) -> &'a mut crate::W<REG> {
634        self.variant(DMAEN1::Enabled)
635    }
636}
637///Field `TSEL2` reader - DAC channel2 trigger selection
638pub use TSEL1_R as TSEL2_R;
639///Field `TSEL2` writer - DAC channel2 trigger selection
640pub use TSEL1_W as TSEL2_W;
641impl R {
642    ///DAC channel(1-2) enable
643    ///
644    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `EN1` field.</div>
645    #[inline(always)]
646    pub fn en(&self, n: u8) -> EN_R {
647        #[allow(clippy::no_effect)]
648        [(); 2][n as usize];
649        EN_R::new(((self.bits >> (n * 16)) & 1) != 0)
650    }
651    ///Iterator for array of:
652    ///DAC channel(1-2) enable
653    #[inline(always)]
654    pub fn en_iter(&self) -> impl Iterator<Item = EN_R> + '_ {
655        (0..2).map(move |n| EN_R::new(((self.bits >> (n * 16)) & 1) != 0))
656    }
657    ///Bit 0 - DAC channel1 enable
658    #[inline(always)]
659    pub fn en1(&self) -> EN_R {
660        EN_R::new((self.bits & 1) != 0)
661    }
662    ///Bit 16 - DAC channel2 enable
663    #[inline(always)]
664    pub fn en2(&self) -> EN_R {
665        EN_R::new(((self.bits >> 16) & 1) != 0)
666    }
667    ///DAC channel(1-2) output buffer disable
668    ///
669    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BOFF1` field.</div>
670    #[inline(always)]
671    pub fn boff(&self, n: u8) -> BOFF_R {
672        #[allow(clippy::no_effect)]
673        [(); 2][n as usize];
674        BOFF_R::new(((self.bits >> (n * 16 + 1)) & 1) != 0)
675    }
676    ///Iterator for array of:
677    ///DAC channel(1-2) output buffer disable
678    #[inline(always)]
679    pub fn boff_iter(&self) -> impl Iterator<Item = BOFF_R> + '_ {
680        (0..2).map(move |n| BOFF_R::new(((self.bits >> (n * 16 + 1)) & 1) != 0))
681    }
682    ///Bit 1 - DAC channel1 output buffer disable
683    #[inline(always)]
684    pub fn boff1(&self) -> BOFF_R {
685        BOFF_R::new(((self.bits >> 1) & 1) != 0)
686    }
687    ///Bit 17 - DAC channel2 output buffer disable
688    #[inline(always)]
689    pub fn boff2(&self) -> BOFF_R {
690        BOFF_R::new(((self.bits >> 17) & 1) != 0)
691    }
692    ///DAC channel(1-2) trigger enable
693    ///
694    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TEN1` field.</div>
695    #[inline(always)]
696    pub fn ten(&self, n: u8) -> TEN_R {
697        #[allow(clippy::no_effect)]
698        [(); 2][n as usize];
699        TEN_R::new(((self.bits >> (n * 16 + 2)) & 1) != 0)
700    }
701    ///Iterator for array of:
702    ///DAC channel(1-2) trigger enable
703    #[inline(always)]
704    pub fn ten_iter(&self) -> impl Iterator<Item = TEN_R> + '_ {
705        (0..2).map(move |n| TEN_R::new(((self.bits >> (n * 16 + 2)) & 1) != 0))
706    }
707    ///Bit 2 - DAC channel1 trigger enable
708    #[inline(always)]
709    pub fn ten1(&self) -> TEN_R {
710        TEN_R::new(((self.bits >> 2) & 1) != 0)
711    }
712    ///Bit 18 - DAC channel2 trigger enable
713    #[inline(always)]
714    pub fn ten2(&self) -> TEN_R {
715        TEN_R::new(((self.bits >> 18) & 1) != 0)
716    }
717    ///Bits 3:5 - DAC channel1 trigger selection
718    #[inline(always)]
719    pub fn tsel1(&self) -> TSEL1_R {
720        TSEL1_R::new(((self.bits >> 3) & 7) as u8)
721    }
722    ///DAC channel(1-2) noise/triangle wave generation enable
723    ///
724    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `WAVE1` field.</div>
725    #[inline(always)]
726    pub fn wave(&self, n: u8) -> WAVE_R {
727        #[allow(clippy::no_effect)]
728        [(); 2][n as usize];
729        WAVE_R::new(((self.bits >> (n * 16 + 6)) & 3) as u8)
730    }
731    ///Iterator for array of:
732    ///DAC channel(1-2) noise/triangle wave generation enable
733    #[inline(always)]
734    pub fn wave_iter(&self) -> impl Iterator<Item = WAVE_R> + '_ {
735        (0..2).map(move |n| WAVE_R::new(((self.bits >> (n * 16 + 6)) & 3) as u8))
736    }
737    ///Bits 6:7 - DAC channel1 noise/triangle wave generation enable
738    #[inline(always)]
739    pub fn wave1(&self) -> WAVE_R {
740        WAVE_R::new(((self.bits >> 6) & 3) as u8)
741    }
742    ///Bits 22:23 - DAC channel2 noise/triangle wave generation enable
743    #[inline(always)]
744    pub fn wave2(&self) -> WAVE_R {
745        WAVE_R::new(((self.bits >> 22) & 3) as u8)
746    }
747    ///DAC channel(1-2) mask/amplitude selector
748    ///
749    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MAMP1` field.</div>
750    #[inline(always)]
751    pub fn mamp(&self, n: u8) -> MAMP_R {
752        #[allow(clippy::no_effect)]
753        [(); 2][n as usize];
754        MAMP_R::new(((self.bits >> (n * 16 + 8)) & 0x0f) as u8)
755    }
756    ///Iterator for array of:
757    ///DAC channel(1-2) mask/amplitude selector
758    #[inline(always)]
759    pub fn mamp_iter(&self) -> impl Iterator<Item = MAMP_R> + '_ {
760        (0..2).map(move |n| MAMP_R::new(((self.bits >> (n * 16 + 8)) & 0x0f) as u8))
761    }
762    ///Bits 8:11 - DAC channel1 mask/amplitude selector
763    #[inline(always)]
764    pub fn mamp1(&self) -> MAMP_R {
765        MAMP_R::new(((self.bits >> 8) & 0x0f) as u8)
766    }
767    ///Bits 24:27 - DAC channel2 mask/amplitude selector
768    #[inline(always)]
769    pub fn mamp2(&self) -> MAMP_R {
770        MAMP_R::new(((self.bits >> 24) & 0x0f) as u8)
771    }
772    ///DAC channel(1-2) DMA enable
773    ///
774    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DMAEN1` field.</div>
775    #[inline(always)]
776    pub fn dmaen(&self, n: u8) -> DMAEN_R {
777        #[allow(clippy::no_effect)]
778        [(); 2][n as usize];
779        DMAEN_R::new(((self.bits >> (n * 16 + 12)) & 1) != 0)
780    }
781    ///Iterator for array of:
782    ///DAC channel(1-2) DMA enable
783    #[inline(always)]
784    pub fn dmaen_iter(&self) -> impl Iterator<Item = DMAEN_R> + '_ {
785        (0..2).map(move |n| DMAEN_R::new(((self.bits >> (n * 16 + 12)) & 1) != 0))
786    }
787    ///Bit 12 - DAC channel1 DMA enable
788    #[inline(always)]
789    pub fn dmaen1(&self) -> DMAEN_R {
790        DMAEN_R::new(((self.bits >> 12) & 1) != 0)
791    }
792    ///Bit 28 - DAC channel2 DMA enable
793    #[inline(always)]
794    pub fn dmaen2(&self) -> DMAEN_R {
795        DMAEN_R::new(((self.bits >> 28) & 1) != 0)
796    }
797    ///Bits 19:21 - DAC channel2 trigger selection
798    #[inline(always)]
799    pub fn tsel2(&self) -> TSEL2_R {
800        TSEL2_R::new(((self.bits >> 19) & 7) as u8)
801    }
802}
803impl core::fmt::Debug for R {
804    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
805        f.debug_struct("CR")
806            .field("en1", &self.en1())
807            .field("en2", &self.en2())
808            .field("boff1", &self.boff1())
809            .field("boff2", &self.boff2())
810            .field("ten1", &self.ten1())
811            .field("ten2", &self.ten2())
812            .field("tsel1", &self.tsel1())
813            .field("wave1", &self.wave1())
814            .field("wave2", &self.wave2())
815            .field("mamp1", &self.mamp1())
816            .field("mamp2", &self.mamp2())
817            .field("dmaen1", &self.dmaen1())
818            .field("dmaen2", &self.dmaen2())
819            .field("tsel2", &self.tsel2())
820            .finish()
821    }
822}
823impl W {
824    ///DAC channel(1-2) enable
825    ///
826    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `EN1` field.</div>
827    #[inline(always)]
828    pub fn en(&mut self, n: u8) -> EN_W<CRrs> {
829        #[allow(clippy::no_effect)]
830        [(); 2][n as usize];
831        EN_W::new(self, n * 16)
832    }
833    ///Bit 0 - DAC channel1 enable
834    #[inline(always)]
835    pub fn en1(&mut self) -> EN_W<CRrs> {
836        EN_W::new(self, 0)
837    }
838    ///Bit 16 - DAC channel2 enable
839    #[inline(always)]
840    pub fn en2(&mut self) -> EN_W<CRrs> {
841        EN_W::new(self, 16)
842    }
843    ///DAC channel(1-2) output buffer disable
844    ///
845    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BOFF1` field.</div>
846    #[inline(always)]
847    pub fn boff(&mut self, n: u8) -> BOFF_W<CRrs> {
848        #[allow(clippy::no_effect)]
849        [(); 2][n as usize];
850        BOFF_W::new(self, n * 16 + 1)
851    }
852    ///Bit 1 - DAC channel1 output buffer disable
853    #[inline(always)]
854    pub fn boff1(&mut self) -> BOFF_W<CRrs> {
855        BOFF_W::new(self, 1)
856    }
857    ///Bit 17 - DAC channel2 output buffer disable
858    #[inline(always)]
859    pub fn boff2(&mut self) -> BOFF_W<CRrs> {
860        BOFF_W::new(self, 17)
861    }
862    ///DAC channel(1-2) trigger enable
863    ///
864    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TEN1` field.</div>
865    #[inline(always)]
866    pub fn ten(&mut self, n: u8) -> TEN_W<CRrs> {
867        #[allow(clippy::no_effect)]
868        [(); 2][n as usize];
869        TEN_W::new(self, n * 16 + 2)
870    }
871    ///Bit 2 - DAC channel1 trigger enable
872    #[inline(always)]
873    pub fn ten1(&mut self) -> TEN_W<CRrs> {
874        TEN_W::new(self, 2)
875    }
876    ///Bit 18 - DAC channel2 trigger enable
877    #[inline(always)]
878    pub fn ten2(&mut self) -> TEN_W<CRrs> {
879        TEN_W::new(self, 18)
880    }
881    ///Bits 3:5 - DAC channel1 trigger selection
882    #[inline(always)]
883    pub fn tsel1(&mut self) -> TSEL1_W<CRrs> {
884        TSEL1_W::new(self, 3)
885    }
886    ///DAC channel(1-2) noise/triangle wave generation enable
887    ///
888    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `WAVE1` field.</div>
889    #[inline(always)]
890    pub fn wave(&mut self, n: u8) -> WAVE_W<CRrs> {
891        #[allow(clippy::no_effect)]
892        [(); 2][n as usize];
893        WAVE_W::new(self, n * 16 + 6)
894    }
895    ///Bits 6:7 - DAC channel1 noise/triangle wave generation enable
896    #[inline(always)]
897    pub fn wave1(&mut self) -> WAVE_W<CRrs> {
898        WAVE_W::new(self, 6)
899    }
900    ///Bits 22:23 - DAC channel2 noise/triangle wave generation enable
901    #[inline(always)]
902    pub fn wave2(&mut self) -> WAVE_W<CRrs> {
903        WAVE_W::new(self, 22)
904    }
905    ///DAC channel(1-2) mask/amplitude selector
906    ///
907    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MAMP1` field.</div>
908    #[inline(always)]
909    pub fn mamp(&mut self, n: u8) -> MAMP_W<CRrs> {
910        #[allow(clippy::no_effect)]
911        [(); 2][n as usize];
912        MAMP_W::new(self, n * 16 + 8)
913    }
914    ///Bits 8:11 - DAC channel1 mask/amplitude selector
915    #[inline(always)]
916    pub fn mamp1(&mut self) -> MAMP_W<CRrs> {
917        MAMP_W::new(self, 8)
918    }
919    ///Bits 24:27 - DAC channel2 mask/amplitude selector
920    #[inline(always)]
921    pub fn mamp2(&mut self) -> MAMP_W<CRrs> {
922        MAMP_W::new(self, 24)
923    }
924    ///DAC channel(1-2) DMA enable
925    ///
926    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DMAEN1` field.</div>
927    #[inline(always)]
928    pub fn dmaen(&mut self, n: u8) -> DMAEN_W<CRrs> {
929        #[allow(clippy::no_effect)]
930        [(); 2][n as usize];
931        DMAEN_W::new(self, n * 16 + 12)
932    }
933    ///Bit 12 - DAC channel1 DMA enable
934    #[inline(always)]
935    pub fn dmaen1(&mut self) -> DMAEN_W<CRrs> {
936        DMAEN_W::new(self, 12)
937    }
938    ///Bit 28 - DAC channel2 DMA enable
939    #[inline(always)]
940    pub fn dmaen2(&mut self) -> DMAEN_W<CRrs> {
941        DMAEN_W::new(self, 28)
942    }
943    ///Bits 19:21 - DAC channel2 trigger selection
944    #[inline(always)]
945    pub fn tsel2(&mut self) -> TSEL2_W<CRrs> {
946        TSEL2_W::new(self, 19)
947    }
948}
949/**Control register (DAC_CR)
950
951You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
952
953See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DAC:CR)*/
954pub struct CRrs;
955impl crate::RegisterSpec for CRrs {
956    type Ux = u32;
957}
958///`read()` method returns [`cr::R`](R) reader structure
959impl crate::Readable for CRrs {}
960///`write(|w| ..)` method takes [`cr::W`](W) writer structure
961impl crate::Writable for CRrs {
962    type Safety = crate::Unsafe;
963}
964///`reset()` method sets CR to value 0
965impl crate::Resettable for CRrs {}
stm32f1/stm32f103/dac/cr.rs

stm32f1/stm32f103/dac/
cr.rs
